From 433c3bb8f972266078aa383281d793f49011a4f7 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sat, 29 Aug 2020 19:17:11 +0800 Subject: [PATCH 01/13] sayma: 1GSPS WIP --- artiq/firmware/libboard_artiq/ad9154.rs | 8 ++--- artiq/firmware/libboard_artiq/hmc830_7043.rs | 32 +++++++++----------- artiq/firmware/runtime/rtio_clocking.rs | 13 -------- artiq/firmware/satman/main.rs | 17 +---------- artiq/gateware/jesd204_tools.py | 24 ++++++--------- artiq/gateware/targets/metlino.py | 2 +- artiq/gateware/targets/sayma_amc.py | 21 ++++++------- artiq/gateware/targets/sayma_rtm.py | 2 +- 8 files changed, 41 insertions(+), 78 deletions(-) diff --git a/artiq/firmware/libboard_artiq/ad9154.rs b/artiq/firmware/libboard_artiq/ad9154.rs index de32ff2e2..f671e2660 100644 --- a/artiq/firmware/libboard_artiq/ad9154.rs +++ b/artiq/firmware/libboard_artiq/ad9154.rs @@ -34,9 +34,9 @@ fn read(addr: u16) -> u8 { } // ad9154 mode 1 -// linerate 5Gbps or 6Gbps -// deviceclock_fpga 125MHz or 150MHz -// deviceclock_dac 500MHz or 600MHz +// linerate 10Gbps +// deviceclock_fpga 125MHz +// deviceclock_dac 1000MHz struct JESDSettings { did: u8, @@ -146,7 +146,7 @@ pub fn setup(dacno: u8, linerate: u64) -> Result<(), &'static str> { write(ad9154_reg::SPI_PAGEINDX, 0x3); // A and B dual - write(ad9154_reg::INTERP_MODE, 0x03); // 4x + write(ad9154_reg::INTERP_MODE, 0x01); // 2x write(ad9154_reg::MIX_MODE, 0); write(ad9154_reg::DATA_FORMAT, 0*ad9154_reg::BINARY_FORMAT); // s16 write(ad9154_reg::DATAPATH_CTRL, diff --git a/artiq/firmware/libboard_artiq/hmc830_7043.rs b/artiq/firmware/libboard_artiq/hmc830_7043.rs index adf753141..d4768aa36 100644 --- a/artiq/firmware/libboard_artiq/hmc830_7043.rs +++ b/artiq/firmware/libboard_artiq/hmc830_7043.rs @@ -149,20 +149,20 @@ pub mod hmc7043 { // enabled, divider, output config, is sysref const OUTPUT_CONFIG: [(bool, u16, u8, bool); 14] = [ - (true, DAC_CLK_DIV, 0x08, false), // 0: DAC1_CLK - (true, SYSREF_DIV, 0x01, true), // 1: DAC1_SYSREF - (true, DAC_CLK_DIV, 0x08, false), // 2: DAC0_CLK - (true, SYSREF_DIV, 0x01, true), // 3: DAC0_SYSREF - (true, SYSREF_DIV, 0x10, true), // 4: AMC_FPGA_SYSREF0 - (false, FPGA_CLK_DIV, 0x10, true), // 5: AMC_FPGA_SYSREF1 - (false, 0, 0x10, false), // 6: unused - (true, FPGA_CLK_DIV, 0x10, true), // 7: RTM_FPGA_SYSREF0 - (true, FPGA_CLK_DIV, 0x08, false), // 8: GTP_CLK0_IN - (false, 0, 0x10, false), // 9: unused - (false, 0, 0x10, false), // 10: unused - (false, 0, 0x08, false), // 11: unused / uFL - (false, 0, 0x10, false), // 12: unused - (false, FPGA_CLK_DIV, 0x10, true), // 13: RTM_FPGA_SYSREF1 + (true, DAC_CLK_DIV, 0x08, false), // 0: DAC1_CLK + (true, SYSREF_DIV, 0x01, true), // 1: DAC1_SYSREF + (true, DAC_CLK_DIV, 0x08, false), // 2: DAC0_CLK + (true, SYSREF_DIV, 0x01, true), // 3: DAC0_SYSREF + (true, SYSREF_DIV, 0x10, true), // 4: AMC_FPGA_SYSREF0 + (false, FPGA_CLK_DIV, 0x10, true), // 5: AMC_FPGA_SYSREF1 + (false, 0, 0x10, false), // 6: unused + (true, FPGA_CLK_DIV, 0x10, true), // 7: RTM_FPGA_SYSREF0 + (true, FPGA_CLK_DIV/2, 0x08, false), // 8: GTP_CLK0_IN + (false, 0, 0x10, false), // 9: unused + (false, 0, 0x10, false), // 10: unused + (false, 0, 0x08, false), // 11: unused / uFL + (false, 0, 0x10, false), // 12: unused + (false, FPGA_CLK_DIV, 0x10, true), // 13: RTM_FPGA_SYSREF1 ]; fn spi_setup() { @@ -393,8 +393,6 @@ pub mod hmc7043 { pub fn init() -> Result<(), &'static str> { #[cfg(all(hmc830_ref = "125", rtio_frequency = "125.0"))] const DIV: (u32, u32, u32, u32) = (2, 32, 0, 1); // 125MHz -> 2.0GHz - #[cfg(all(hmc830_ref = "150", rtio_frequency = "150.0"))] - const DIV: (u32, u32, u32, u32) = (2, 32, 0, 1); // 150MHz -> 2.4GHz /* do not use other SPI devices before HMC830 SPI mode selection */ hmc830::select_spi_mode(); @@ -406,7 +404,7 @@ pub fn init() -> Result<(), &'static str> { hmc830::check_locked()?; if hmc7043::get_id() == hmc7043::CHIP_ID { - error!("HMC7043 detected while in reset (board rework missing?)"); + error!("HMC7043 detected while in reset"); } hmc7043::enable(); hmc7043::detect()?; diff --git a/artiq/firmware/runtime/rtio_clocking.rs b/artiq/firmware/runtime/rtio_clocking.rs index 0a41ab8d0..c5501a755 100644 --- a/artiq/firmware/runtime/rtio_clocking.rs +++ b/artiq/firmware/runtime/rtio_clocking.rs @@ -119,19 +119,6 @@ fn setup_si5324_as_synthesizer() { bwsel : 4, crystal_ref: true }; - // 150MHz output, from crystal - #[cfg(all(rtio_frequency = "150.0", not(si5324_ext_ref)))] - const SI5324_SETTINGS: si5324::FrequencySettings - = si5324::FrequencySettings { - n1_hs : 9, - nc1_ls : 4, - n2_hs : 10, - n2_ls : 33732, - n31 : 9370, - n32 : 7139, - bwsel : 3, - crystal_ref: true - }; // 100MHz output, from crystal. Also used as reference for Sayma HMC830. #[cfg(all(rtio_frequency = "100.0", not(si5324_ext_ref)))] const SI5324_SETTINGS: si5324::FrequencySettings diff --git a/artiq/firmware/satman/main.rs b/artiq/firmware/satman/main.rs index 60f0f4c0a..ac16a116c 100644 --- a/artiq/firmware/satman/main.rs +++ b/artiq/firmware/satman/main.rs @@ -302,9 +302,7 @@ fn process_aux_packet(_repeaters: &mut [repeater::Repeater], #[cfg(has_ad9154)] let (succeeded, retval) = { #[cfg(rtio_frequency = "125.0")] - const LINERATE: u64 = 5_000_000_000; - #[cfg(rtio_frequency = "150.0")] - const LINERATE: u64 = 6_000_000_000; + const LINERATE: u64 = 10_000_000_000; match _reqno { jdac_common::INIT => (board_artiq::ad9154::setup(_dacno, LINERATE).is_ok(), 0), jdac_common::PRINT_STATUS => { board_artiq::ad9154::status(_dacno); (true, 0) }, @@ -419,19 +417,6 @@ fn hardware_tick(ts: &mut u64) { } } -#[cfg(all(has_si5324, rtio_frequency = "150.0"))] -const SI5324_SETTINGS: si5324::FrequencySettings - = si5324::FrequencySettings { - n1_hs : 6, - nc1_ls : 6, - n2_hs : 10, - n2_ls : 270, - n31 : 75, - n32 : 75, - bwsel : 4, - crystal_ref: true -}; - #[cfg(all(has_si5324, rtio_frequency = "125.0"))] const SI5324_SETTINGS: si5324::FrequencySettings = si5324::FrequencySettings { diff --git a/artiq/gateware/jesd204_tools.py b/artiq/gateware/jesd204_tools.py index 27a1ce6cc..8cd8e9872 100644 --- a/artiq/gateware/jesd204_tools.py +++ b/artiq/gateware/jesd204_tools.py @@ -15,30 +15,26 @@ from jesd204b.core import JESD204BCoreTXControl class UltrascaleCRG(Module, AutoCSR): - linerate = int(6e9) - refclk_freq = int(150e6) + linerate = int(10e9) # linerate = 20*data_rate*4/8 = data_rate*10 + refclk_freq = int(250e6) fabric_freq = int(125e6) - def __init__(self, platform, use_rtio_clock=False): + def __init__(self, platform): self.jreset = CSRStorage(reset=1) self.refclk = Signal() self.clock_domains.cd_jesd = ClockDomain() - refclk2 = Signal() refclk_pads = platform.request("dac_refclk", 0) platform.add_period_constraint(refclk_pads.p, 1e9/self.refclk_freq) self.specials += [ - Instance("IBUFDS_GTE3", i_CEB=0, p_REFCLK_HROW_CK_SEL=0b00, + Instance("IBUFDS_GTE3", i_CEB=0, p_REFCLK_HROW_CK_SEL=0b01, i_I=refclk_pads.p, i_IB=refclk_pads.n, - o_O=self.refclk, o_ODIV2=refclk2), - AsyncResetSynchronizer(self.cd_jesd, self.jreset.storage), + o_O=self.refclk), ] - if use_rtio_clock: - self.cd_jesd.clk.attr.add("keep") - self.comb += self.cd_jesd.clk.eq(ClockSignal("rtio")) - else: - self.specials += Instance("BUFG_GT", i_I=refclk2, o_O=self.cd_jesd.clk) + self.cd_jesd.clk.attr.add("keep") + self.comb += self.cd_jesd.clk.eq(ClockSignal("rtio")) + self.specials += AsyncResetSynchronizer(self.cd_jesd, self.jreset.storage) PhyPads = namedtuple("PhyPads", "txp txn") @@ -68,7 +64,7 @@ class UltrascaleTX(Module, AutoCSR): phys.append(phy) self.submodules.core = JESD204BCoreTX( - phys, settings, converter_data_width=64) + phys, settings, converter_data_width=128) self.submodules.control = JESD204BCoreTXControl(self.core) self.core.register_jsync(platform.request("dac_sync", dac)) @@ -92,7 +88,7 @@ class DDMTDEdgeDetector(Module): # See "Digital femtosecond time difference circuit for CERN's timing system" # by P. Moreira and I. Darwazeh class DDMTD(Module, AutoCSR): - def __init__(self, input_pads, rtio_clk_freq=150e6): + def __init__(self, input_pads, rtio_clk_freq=125e6): N = 64 self.reset = CSRStorage(reset=1) self.locked = CSRStatus() diff --git a/artiq/gateware/targets/metlino.py b/artiq/gateware/targets/metlino.py index d1013653c..66afbf0eb 100755 --- a/artiq/gateware/targets/metlino.py +++ b/artiq/gateware/targets/metlino.py @@ -52,7 +52,7 @@ class Master(MiniSoC, AMPSoC): add_identifier(self) platform = self.platform - rtio_clk_freq = 150e6 + rtio_clk_freq = 125e6 self.comb += platform.request("input_clk_sel").eq(1) self.comb += platform.request("filtered_clk_sel").eq(1) diff --git a/artiq/gateware/targets/sayma_amc.py b/artiq/gateware/targets/sayma_amc.py index c2cb435f1..841e28b89 100755 --- a/artiq/gateware/targets/sayma_amc.py +++ b/artiq/gateware/targets/sayma_amc.py @@ -193,7 +193,7 @@ class JDCGSAWG(Module, AutoCSR): self.submodules.jesd = jesd204_tools.UltrascaleTX( platform, sys_crg, jesd_crg, dac) - self.submodules.sawgs = [sawg.Channel(width=16, parallelism=4) for i in range(4)] + self.submodules.sawgs = [sawg.Channel(width=16, parallelism=8) for i in range(4)] for conv, ch in zip(self.jesd.core.sink.flatten(), self.sawgs): assert len(Cat(ch.o)) == len(conv) @@ -210,26 +210,26 @@ class JDCGPattern(Module, AutoCSR): ramp = Signal(4) self.sync.rtio += ramp.eq(ramp + 1) - samples = [[Signal(16) for i in range(4)] for j in range(4)] + samples = [[Signal(16) for i in range(8)] for j in range(4)] self.comb += [ a.eq(Cat(b)) for a, b in zip( self.jesd.core.sink.flatten(), samples) ] # ch0: 16-step ramp with big carry toggles - for i in range(4): + for i in range(8): self.comb += [ samples[0][i][-4:].eq(ramp), samples[0][i][:-4].eq(0x7ff if i % 2 else 0x800) ] # ch1: 50 MHz from math import pi, cos - data = [int(round(cos(i/12*2*pi)*((1 << 15) - 1))) - for i in range(12)] + data = [int(round(cos(i/24*2*pi)*((1 << 15) - 1))) + for i in range(24)] k = Signal(2) self.sync.rtio += If(k == 2, k.eq(0)).Else(k.eq(k + 1)) self.comb += [ Case(k, { - i: [samples[1][j].eq(data[i*4 + j]) for j in range(4)] + i: [samples[1][j].eq(data[i*8 + j]) for j in range(8)] for i in range(3) }) ] @@ -249,7 +249,7 @@ class JDCGSyncDDS(Module, AutoCSR): self.sawgs = [] ftw = round(2**len(self.coarse_ts)*9e6/600e6) - parallelism = 4 + parallelism = 8 mul_1 = Signal.like(self.coarse_ts) mul_2 = Signal.like(self.coarse_ts) @@ -287,9 +287,7 @@ class Satellite(SatelliteBase): DRTIO satellite with local DAC/SAWG channels. """ def __init__(self, jdcg_type, **kwargs): - SatelliteBase.__init__(self, 150e6, - identifier_suffix="." + jdcg_type, - **kwargs) + SatelliteBase.__init__(self, identifier_suffix="." + jdcg_type, **kwargs) platform = self.platform @@ -323,8 +321,7 @@ class Satellite(SatelliteBase): self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) - self.submodules.jesd_crg = jesd204_tools.UltrascaleCRG( - platform, use_rtio_clock=True) + self.submodules.jesd_crg = jesd204_tools.UltrascaleCRG(platform) cls = { "sawg": JDCGSAWG, "pattern": JDCGPattern, diff --git a/artiq/gateware/targets/sayma_rtm.py b/artiq/gateware/targets/sayma_rtm.py index bdef1fa09..82b09699f 100755 --- a/artiq/gateware/targets/sayma_rtm.py +++ b/artiq/gateware/targets/sayma_rtm.py @@ -297,7 +297,7 @@ def main(): builder_args(parser) soc_sayma_rtm_args(parser) parser.add_argument("--rtio-clk-freq", - default=150, type=int, help="RTIO clock frequency in MHz") + default=125, type=int, help="RTIO clock frequency in MHz") parser.add_argument("--with-wrpll", default=False, action="store_true") parser.set_defaults(output_dir=os.path.join("artiq_sayma", "rtm")) args = parser.parse_args() From b5405dfad6a3f3e375003a63baa90bf3473776ce Mon Sep 17 00:00:00 2001 From: Harry Ho Date: Tue, 15 Dec 2020 17:55:48 +0800 Subject: [PATCH 02/13] jdcg: STPL tests now perform after DAC initialization --- artiq/firmware/satman/jdcg.rs | 21 ++++++++++++++++----- artiq/firmware/satman/main.rs | 1 + 2 files changed, 17 insertions(+), 5 deletions(-) diff --git a/artiq/firmware/satman/jdcg.rs b/artiq/firmware/satman/jdcg.rs index c581791a3..c8a34827b 100644 --- a/artiq/firmware/satman/jdcg.rs +++ b/artiq/firmware/satman/jdcg.rs @@ -108,10 +108,6 @@ pub mod jdac { basic_request(dacno, jdac_common::PRBS, 0)?; jesd::prbs(dacno, false); - jesd::stpl(dacno, true); - basic_request(dacno, jdac_common::STPL, 0)?; - jesd::stpl(dacno, false); - basic_request(dacno, jdac_common::INIT, 0)?; clock::spin_us(5000); @@ -120,7 +116,22 @@ pub mod jdac { return Err("JESD core reported bad SYNC"); } - info!(" ...done"); + info!(" ...done initializing"); + } + Ok(()) + } + + pub fn stpl() -> Result<(), &'static str> { + for dacno in 0..csr::JDCG.len() { + let dacno = dacno as u8; + + info!("Running STPL test on DAC-{}...", dacno); + + jesd::stpl(dacno, true); + basic_request(dacno, jdac_common::STPL, 0)?; + jesd::stpl(dacno, false); + + info!(" ...done STPL test"); } Ok(()) } diff --git a/artiq/firmware/satman/main.rs b/artiq/firmware/satman/main.rs index ac16a116c..2abaa2d12 100644 --- a/artiq/firmware/satman/main.rs +++ b/artiq/firmware/satman/main.rs @@ -594,6 +594,7 @@ pub extern fn main() -> i32 { jdcg::jesd::reset(false); let _ = jdcg::jdac::init(); jdcg::jesd204sync::sysref_auto_align(); + jdcg::jdac::stpl(); unsafe { csr::drtio_transceiver::txenable_write(0xffffffffu32 as _); // unhide } From 400af2c582316b7f94e442ed4eaeb74a95ae1275 Mon Sep 17 00:00:00 2001 From: Harry Ho Date: Tue, 15 Dec 2020 17:55:59 +0800 Subject: [PATCH 03/13] sayma: use QPLL for 1GSPS JESD204B TX * requires jesd204b changes as in https://github.com/HarryMakes/jesd204b/tree/gth --- artiq/firmware/libboard_artiq/ad9154.rs | 24 +++++- artiq/gateware/jesd204_tools.py | 106 ++++++++++++++++++++---- artiq/gateware/targets/sayma_amc.py | 8 +- 3 files changed, 118 insertions(+), 20 deletions(-) diff --git a/artiq/firmware/libboard_artiq/ad9154.rs b/artiq/firmware/libboard_artiq/ad9154.rs index f671e2660..388c8ac9a 100644 --- a/artiq/firmware/libboard_artiq/ad9154.rs +++ b/artiq/firmware/libboard_artiq/ad9154.rs @@ -87,7 +87,7 @@ const JESD_SETTINGS: JESDSettings = JESDSettings { np: 16, f: 2, s: 2, - k: 16, + k: 32, cs: 0, subclassv: 1, @@ -349,6 +349,28 @@ pub fn setup(dacno: u8, linerate: u64) -> Result<(), &'static str> { write(ad9154_reg::GENERAL_JRX_CTRL_0, 0x1*ad9154_reg::LINK_EN | 0*ad9154_reg::LINK_PAGE | 0*ad9154_reg::LINK_MODE | 0*ad9154_reg::CHECKSUM_MODE); + + // JESD Checks + let jesd_checks = read(ad9154_reg::JESD_CHECKS); + if jesd_checks & ad9154_reg::ERR_DLYOVER == ad9154_reg::ERR_DLYOVER { + error!("LMFC_Delay > JESD_K Parameter") + } + if jesd_checks & ad9154_reg::ERR_WINLIMIT == ad9154_reg::ERR_WINLIMIT { + error!("Unsupported Window Limit") + } + if jesd_checks & ad9154_reg::ERR_JESDBAD == ad9154_reg::ERR_JESDBAD { + error!("Unsupported M/L/S/F Selection") + } + if jesd_checks & ad9154_reg::ERR_KUNSUPP == ad9154_reg::ERR_KUNSUPP { + error!("Unsupported K Values") + } + if jesd_checks & ad9154_reg::ERR_SUBCLASS == ad9154_reg::ERR_SUBCLASS { + error!("Unsupported SUBCLASSV Value") + } + if jesd_checks & ad9154_reg::ERR_INTSUPP == ad9154_reg::ERR_INTSUPP { + error!("Unsupported Interpolation Factor") + } + info!(" ...done"); Ok(()) } diff --git a/artiq/gateware/jesd204_tools.py b/artiq/gateware/jesd204_tools.py index 8cd8e9872..6baa07f15 100644 --- a/artiq/gateware/jesd204_tools.py +++ b/artiq/gateware/jesd204_tools.py @@ -8,7 +8,11 @@ from misoc.interconnect.csr import * from jesd204b.common import (JESD204BTransportSettings, JESD204BPhysicalSettings, JESD204BSettings) -from jesd204b.phy.gth import GTHChannelPLL as JESD204BGTHChannelPLL +from jesd204b.phy.gth import (GTHChannelPLL as JESD204BGTHChannelPLL, + GTHQuadPLL as JESD204BGTHQuadPLL, + GTHTransmitter as JESD204BGTHTransmitter, + GTHInit as JESD204BGTHInit, + GTHTransmitterInterconnect as JESD204BGTHTransmitterInterconnect) from jesd204b.phy import JESD204BPhyTX from jesd204b.core import JESD204BCoreTX from jesd204b.core import JESD204BCoreTXControl @@ -16,6 +20,7 @@ from jesd204b.core import JESD204BCoreTXControl class UltrascaleCRG(Module, AutoCSR): linerate = int(10e9) # linerate = 20*data_rate*4/8 = data_rate*10 + # data_rate = dac_rate/interp_factor refclk_freq = int(250e6) fabric_freq = int(125e6) @@ -41,30 +46,99 @@ PhyPads = namedtuple("PhyPads", "txp txn") class UltrascaleTX(Module, AutoCSR): - def __init__(self, platform, sys_crg, jesd_crg, dac): + def __init__(self, platform, sys_crg, jesd_crg, dac, pll_type="cpll", tx_half=False): + # Note: In general, the choice between channel and quad PLLs can be made based on the "nominal operating ranges", which are (see UG576, Ch.2): + # CPLL: 2.0 - 6.25 GHz + # QPLL0: 9.8 - 16.375 GHz + # QPLL1: 8.0 - 13.0 GHz + # However, the exact frequency and/or linerate range should be checked according to the model and speed grade from their corresponding datasheets. + pll_cls = { + "cpll": JESD204BGTHChannelPLL, + "qpll": JESD204BGTHQuadPLL + }[pll_type] ps = JESD204BPhysicalSettings(l=8, m=4, n=16, np=16) - ts = JESD204BTransportSettings(f=2, s=2, k=16, cs=0) + ts = JESD204BTransportSettings(f=2, s=2, k=32, cs=0) settings = JESD204BSettings(ps, ts, did=0x5a, bid=0x5) jesd_pads = platform.request("dac_jesd", dac) + plls = [] phys = [] for i in range(len(jesd_pads.txp)): - cpll = JESD204BGTHChannelPLL( - jesd_crg.refclk, jesd_crg.refclk_freq, jesd_crg.linerate) - self.submodules += cpll + pll = pll_cls( + jesd_crg.refclk, jesd_crg.refclk_freq, jesd_crg.linerate) + self.submodules += pll + plls.append(pll) + # QPLL quads + if pll_type == "qpll": + gthe3_common_cfgs = [] + for i in range(0, len(plls), 4): + # GTHE3_COMMON common signals + qpll_clk = Signal() + qpll_refclk = Signal() + qpll_reset = Signal() + qpll_lock = Signal() + # GTHE3_COMMON + self.specials += pll_cls.get_gthe3_common( + jesd_crg.refclk, jesd_crg.refclk_freq, jesd_crg.linerate, + qpll_clk, qpll_refclk, qpll_reset, qpll_lock) + gthe3_common_cfgs.append({ + "clk": qpll_clk, + "refclk": qpll_refclk, + "reset": qpll_reset, + "lock": qpll_lock + }) + # Per-channel PLL phys + for i, pll in enumerate(plls): + # PhyTX phy = JESD204BPhyTX( - cpll, PhyPads(jesd_pads.txp[i], jesd_pads.txn[i]), - jesd_crg.fabric_freq, transceiver="gth") - platform.add_period_constraint(phy.transmitter.cd_tx.clk, - 40*1e9/jesd_crg.linerate) - platform.add_false_path_constraints( - sys_crg.cd_sys.clk, - jesd_crg.cd_jesd.clk, - phy.transmitter.cd_tx.clk) + pll, jesd_crg.refclk, PhyPads(jesd_pads.txp[i], jesd_pads.txn[i]), + jesd_crg.fabric_freq, transceiver="gth", tx_half=tx_half) phys.append(phy) + if tx_half: + platform.add_period_constraint(phy.transmitter.cd_tx_half.clk, + 80*1e9/jesd_crg.linerate) + platform.add_false_path_constraints( + sys_crg.cd_sys.clk, + jesd_crg.cd_jesd.clk, + phy.transmitter.cd_tx_half.clk) + else: + platform.add_period_constraint(phy.transmitter.cd_tx.clk, + 40*1e9/jesd_crg.linerate) + platform.add_false_path_constraints( + sys_crg.cd_sys.clk, + jesd_crg.cd_jesd.clk, + phy.transmitter.cd_tx.clk) + # CHANNEL & init interconnects + for i, (pll, phy) in enumerate(zip(plls, phys)): + # CPLLs: 1 init per channel + if pll_type == "cpll": + phy_channel_cfg = {} + # Connect reset/lock to init + pll_reset = pll.reset + pll_lock = pll.lock + self.submodules += JESD204BGTHTransmitterInterconnect( + pll_reset, pll_lock, phy.transmitter, phy.transmitter.init) + # QPLL: 4 inits and 4 channels per quad + elif pll_type == "qpll": + # Connect clk/refclk to CHANNEL + phy_cfg = gthe3_common_cfgs[int(i//4)] + phy_channel_cfg = { + "qpll_clk": phy_cfg["clk"], + "qpll_refclk": phy_cfg["refclk"] + } + # Connect reset/lock to init + pll_reset = phy_cfg["reset"] + pll_lock = phy_cfg["lock"] + if i % 4 == 0: + self.submodules += JESD204BGTHTransmitterInterconnect( + pll_reset, pll_lock, phy.transmitter, + [phys[j].transmitter.init for j in range(i, min(len(phys), i+4))]) + # GTHE3_CHANNEL + self.specials += JESD204BGTHTransmitter.get_gthe3_channel( + pll, phy.transmitter, **phy_channel_cfg) self.submodules.core = JESD204BCoreTX( - phys, settings, converter_data_width=128) + phys, settings, converter_data_width=128, tx_half=tx_half) self.submodules.control = JESD204BCoreTXControl(self.core) self.core.register_jsync(platform.request("dac_sync", dac)) @@ -111,7 +185,7 @@ class DDMTD(Module, AutoCSR): i_RST=self.reset.storage, o_LOCKED=helper_locked, - # VCO at 1200MHz with 150MHz RTIO frequency + # VCO at 1000MHz/1200MHz with 125MHz/150MHz RTIO frequency p_CLKFBOUT_MULT_F=8.0, p_DIVCLK_DIVIDE=1, diff --git a/artiq/gateware/targets/sayma_amc.py b/artiq/gateware/targets/sayma_amc.py index 841e28b89..868c4f1f4 100755 --- a/artiq/gateware/targets/sayma_amc.py +++ b/artiq/gateware/targets/sayma_amc.py @@ -190,8 +190,10 @@ class SatelliteBase(MiniSoC): # JESD204 DAC Channel Group class JDCGSAWG(Module, AutoCSR): def __init__(self, platform, sys_crg, jesd_crg, dac): + # Kintex Ultrascale GTH, speed grade -1C: + # QPLL0 linerate (D=1): 9.8 - 12.5 Gb/s self.submodules.jesd = jesd204_tools.UltrascaleTX( - platform, sys_crg, jesd_crg, dac) + platform, sys_crg, jesd_crg, dac, pll_type="qpll", tx_half=True) self.submodules.sawgs = [sawg.Channel(width=16, parallelism=8) for i in range(4)] @@ -203,7 +205,7 @@ class JDCGSAWG(Module, AutoCSR): class JDCGPattern(Module, AutoCSR): def __init__(self, platform, sys_crg, jesd_crg, dac): self.submodules.jesd = jesd204_tools.UltrascaleTX( - platform, sys_crg, jesd_crg, dac) + platform, sys_crg, jesd_crg, dac, pll_type="qpll", tx_half=True) self.sawgs = [] @@ -243,7 +245,7 @@ class JDCGPattern(Module, AutoCSR): class JDCGSyncDDS(Module, AutoCSR): def __init__(self, platform, sys_crg, jesd_crg, dac): self.submodules.jesd = jesd204_tools.UltrascaleTX( - platform, sys_crg, jesd_crg, dac) + platform, sys_crg, jesd_crg, dac, pll_type="qpll", tx_half=True) self.coarse_ts = Signal(32) self.sawgs = [] From d74cd24d89261aafaee754cb02776dc31b98d274 Mon Sep 17 00:00:00 2001 From: Harry Ho Date: Tue, 15 Dec 2020 17:56:05 +0800 Subject: [PATCH 04/13] sayma_amc: fix JDCGPattern data for 1Gsps --- artiq/gateware/targets/sayma_amc.py | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/artiq/gateware/targets/sayma_amc.py b/artiq/gateware/targets/sayma_amc.py index 868c4f1f4..55c507989 100755 --- a/artiq/gateware/targets/sayma_amc.py +++ b/artiq/gateware/targets/sayma_amc.py @@ -224,15 +224,23 @@ class JDCGPattern(Module, AutoCSR): samples[0][i][:-4].eq(0x7ff if i % 2 else 0x800) ] # ch1: 50 MHz + # - Formulae: + # target cosine wave frequency: f = 50e6 + # DAC sampling frequency: fs = 1000e6 + # number of samples per coarse RTIO period: P = 8 + # number of samples needed per wave period: M = (1/f) / (1/fs)) = 20 + # number of repeating samples needed: N = LCM(P, M) = 40 + # number of RTIO periods needed for repeating: k = N/P = 5 + # discretized value of the wave: y[i] = cos(i/M * 2pi) from math import pi, cos - data = [int(round(cos(i/24*2*pi)*((1 << 15) - 1))) - for i in range(24)] - k = Signal(2) - self.sync.rtio += If(k == 2, k.eq(0)).Else(k.eq(k + 1)) + data = [int(round(cos(i/20*2*pi)*((1 << 15) - 1))) + for i in range(40)] + k = Signal(max=5) + self.sync.rtio += If(k == 4, k.eq(0)).Else(k.eq(k + 1)) self.comb += [ Case(k, { i: [samples[1][j].eq(data[i*8 + j]) for j in range(8)] - for i in range(3) + for i in range(5) }) ] # ch2: ch0, ch3: ch1 From 9dfb0bfe1b77dfd2706a40f48cf174cd97c07eb4 Mon Sep 17 00:00:00 2001 From: Harry Ho Date: Thu, 16 Sep 2021 11:39:59 +0800 Subject: [PATCH 05/13] gth_ultrascale: fix missing T/RXPROGDIVRESET --- artiq/gateware/drtio/transceiver/gth_ultrascale.py | 4 ++-- artiq/gateware/drtio/transceiver/gth_ultrascale_init.py | 5 +++++ 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/artiq/gateware/drtio/transceiver/gth_ultrascale.py b/artiq/gateware/drtio/transceiver/gth_ultrascale.py index ddc88037a..0bf4e9e4c 100644 --- a/artiq/gateware/drtio/transceiver/gth_ultrascale.py +++ b/artiq/gateware/drtio/transceiver/gth_ultrascale.py @@ -77,8 +77,6 @@ class GTHSingle(Module): p_ALIGN_PCOMMA_DET ="FALSE", p_ALIGN_PCOMMA_VALUE =0b0101111100, p_A_RXOSCALRESET =0b0, - p_A_RXPROGDIVRESET =0b0, - p_A_TXPROGDIVRESET =0b0, p_CBCC_DATA_SOURCE_SEL ="ENCODED", p_CDR_SWAP_MODE_EN =0b0, p_CHAN_BOND_KEEP_ALIGN ="FALSE", @@ -475,6 +473,7 @@ class GTHSingle(Module): # TX Startup/Reset i_GTTXRESET=tx_init.gtXxreset, + i_TXPROGDIVRESET=tx_init.gtXxprogdivreset, o_TXRESETDONE=tx_init.Xxresetdone, i_TXDLYSRESET=tx_init.Xxdlysreset if mode != "slave" else self.txdlysreset, o_TXDLYSRESETDONE=tx_init.Xxdlysresetdone, @@ -501,6 +500,7 @@ class GTHSingle(Module): # RX Startup/Reset i_GTRXRESET=rx_init.gtXxreset, + i_RXPROGDIVRESET=rx_init.gtXxprogdivreset, o_RXRESETDONE=rx_init.Xxresetdone, i_RXDLYSRESET=rx_init.Xxdlysreset, o_RXPHALIGNDONE=rxphaligndone, diff --git a/artiq/gateware/drtio/transceiver/gth_ultrascale_init.py b/artiq/gateware/drtio/transceiver/gth_ultrascale_init.py index 30645b876..6e4e80d59 100644 --- a/artiq/gateware/drtio/transceiver/gth_ultrascale_init.py +++ b/artiq/gateware/drtio/transceiver/gth_ultrascale_init.py @@ -18,6 +18,8 @@ class GTHInit(Module): self.plllock = Signal() self.pllreset = Signal() self.gtXxreset = Signal() + # Reset signal for programmable divider: https://www.xilinx.com/support/answers/64103.html + self.gtXxprogdivreset = Signal() self.Xxresetdone = Signal() self.Xxdlysreset = Signal() self.Xxdlysresetdone = Signal() @@ -46,10 +48,12 @@ class GTHInit(Module): # Deglitch FSM outputs driving transceiver asynch inputs gtXxreset = Signal() + gtXxprogdivreset = Signal() Xxdlysreset = Signal() Xxuserrdy = Signal() self.sync += [ self.gtXxreset.eq(gtXxreset), + self.gtXxprogdivreset.eq(gtXxprogdivreset), self.Xxdlysreset.eq(Xxdlysreset), self.Xxuserrdy.eq(Xxuserrdy) ] @@ -80,6 +84,7 @@ class GTHInit(Module): startup_fsm.act("RESET_ALL", gtXxreset.eq(1), + gtXxprogdivreset.eq(1), self.pllreset.eq(1), pll_reset_timer.wait.eq(1), If(pll_reset_timer.done, From f5b9eab84b2b0aa065cc23d5cf1f90c522a3db31 Mon Sep 17 00:00:00 2001 From: Harry Ho Date: Thu, 16 Sep 2021 11:40:09 +0800 Subject: [PATCH 06/13] ad9154: fix sync --- artiq/firmware/libboard_artiq/ad9154.rs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/artiq/firmware/libboard_artiq/ad9154.rs b/artiq/firmware/libboard_artiq/ad9154.rs index de32ff2e2..d6d3b2c02 100644 --- a/artiq/firmware/libboard_artiq/ad9154.rs +++ b/artiq/firmware/libboard_artiq/ad9154.rs @@ -144,8 +144,6 @@ pub fn setup(dacno: u8, linerate: u64) -> Result<(), &'static str> { write(ad9154_reg::DEVICE_CONFIG_REG_1, 0x01); // magic write(ad9154_reg::DEVICE_CONFIG_REG_2, 0x01); // magic - write(ad9154_reg::SPI_PAGEINDX, 0x3); // A and B dual - write(ad9154_reg::INTERP_MODE, 0x03); // 4x write(ad9154_reg::MIX_MODE, 0); write(ad9154_reg::DATA_FORMAT, 0*ad9154_reg::BINARY_FORMAT); // s16 @@ -333,6 +331,7 @@ pub fn setup(dacno: u8, linerate: u64) -> Result<(), &'static str> { write(ad9154_reg::SYNC_ERRWINDOW, 0); // +- 1/2 DAC clock // datasheet seems to say ENABLE and ARM should be separate steps, // so enable now so it can be armed in sync(). + write(ad9154_reg::SPI_PAGEINDX, 0x3); // A and B dual write(ad9154_reg::SYNC_CONTROL, 0x1*ad9154_reg::SYNCMODE | 1*ad9154_reg::SYNCENABLE | 0*ad9154_reg::SYNCARM | 0*ad9154_reg::SYNCCLRSTKY); @@ -529,6 +528,7 @@ pub fn stpl(dacno: u8, m: u8, s: u8) -> Result<(), &'static str> { pub fn sync(dacno: u8) -> Result { spi_setup(dacno); + write(ad9154_reg::SPI_PAGEINDX, 0x3); // A and B dual write(ad9154_reg::SYNC_CONTROL, 0x1*ad9154_reg::SYNCMODE | 1*ad9154_reg::SYNCENABLE | 1*ad9154_reg::SYNCARM | 1*ad9154_reg::SYNCCLRSTKY); From 51e28de2f61a978481d27824073567142ae657d2 Mon Sep 17 00:00:00 2001 From: Harry Ho Date: Thu, 16 Sep 2021 15:37:46 +0800 Subject: [PATCH 07/13] ad9154: check alignment phase error after one-shot sync --- artiq/firmware/libboard_artiq/ad9154.rs | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/artiq/firmware/libboard_artiq/ad9154.rs b/artiq/firmware/libboard_artiq/ad9154.rs index d6d3b2c02..493f1593a 100644 --- a/artiq/firmware/libboard_artiq/ad9154.rs +++ b/artiq/firmware/libboard_artiq/ad9154.rs @@ -545,5 +545,10 @@ pub fn sync(dacno: u8) -> Result { return Err("no sysref edge"); } let realign_occured = sync_status & ad9154_reg::SYNC_ROTATE != 0; + let phase_error = sync_status & ad9154_reg::SYNC_WLIM != 0; + if !realign_occured && phase_error { + // see also: SYNC_ERRWINDOW + warn!(" phase error window exceeded but clock did not rotate"); + } Ok(realign_occured) } From 412936f8dbf4e7fd0d2221ddd765bbe8c0bdf028 Mon Sep 17 00:00:00 2001 From: Harry Ho Date: Mon, 4 Oct 2021 17:03:59 +0800 Subject: [PATCH 08/13] ad9154: adjust LMFCDel & LMFCVar based on DYN_LINK_LATENCY readbacks * @HarryMakes performed 25 consecutive power-cycles of Sayma, in 2-min intervals: * Results: MinDelay = 6, FALL_COUNT_Delay = 8 (w/ rollover) --- artiq/firmware/libboard_artiq/ad9154.rs | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/artiq/firmware/libboard_artiq/ad9154.rs b/artiq/firmware/libboard_artiq/ad9154.rs index 493f1593a..d10ae53b3 100644 --- a/artiq/firmware/libboard_artiq/ad9154.rs +++ b/artiq/firmware/libboard_artiq/ad9154.rs @@ -324,10 +324,13 @@ pub fn setup(dacno: u8, linerate: u64) -> Result<(), &'static str> { 1*ad9154_reg::EQ_POWER_MODE); write(ad9154_reg::GENERAL_JRX_CTRL_1, 1); // subclass 1 - write(ad9154_reg::LMFC_DELAY_0, 0); - write(ad9154_reg::LMFC_DELAY_1, 0); - write(ad9154_reg::LMFC_VAR_0, 0x0a); // receive buffer delay - write(ad9154_reg::LMFC_VAR_1, 0x0a); + // LMFCDel & LMFCVar were deduced from values of DYN_LINK_LATENCY_0 + // gathered from repeated power-cycles; see datasheet (Rev. C) p.44 + // "Link Delay Setup Example, Without Known Delay" + write(ad9154_reg::LMFC_DELAY_0, 10); + write(ad9154_reg::LMFC_DELAY_1, 10); + write(ad9154_reg::LMFC_VAR_0, 4); // receive buffer delay + write(ad9154_reg::LMFC_VAR_1, 4); write(ad9154_reg::SYNC_ERRWINDOW, 0); // +- 1/2 DAC clock // datasheet seems to say ENABLE and ARM should be separate steps, // so enable now so it can be armed in sync(). From a14666bc1559223ed00be6cd8af602e32c76dd4f Mon Sep 17 00:00:00 2001 From: Harry Ho Date: Mon, 6 Dec 2021 17:52:50 +0800 Subject: [PATCH 09/13] ad9154: re-adjust LMFCDel & LMFCVar for 1 GS/s (K=32) * @HarryMakes performed 25 consecutive power-cycles of Sayma, in 2-min intervals: * Results: MinDelay = 8, FALL_COUNT_Delay = 10 --- artiq/firmware/libboard_artiq/ad9154.rs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/artiq/firmware/libboard_artiq/ad9154.rs b/artiq/firmware/libboard_artiq/ad9154.rs index 717a06eb5..d232dcafc 100644 --- a/artiq/firmware/libboard_artiq/ad9154.rs +++ b/artiq/firmware/libboard_artiq/ad9154.rs @@ -327,8 +327,8 @@ pub fn setup(dacno: u8, linerate: u64) -> Result<(), &'static str> { // LMFCDel & LMFCVar were deduced from values of DYN_LINK_LATENCY_0 // gathered from repeated power-cycles; see datasheet (Rev. C) p.44 // "Link Delay Setup Example, Without Known Delay" - write(ad9154_reg::LMFC_DELAY_0, 10); - write(ad9154_reg::LMFC_DELAY_1, 10); + write(ad9154_reg::LMFC_DELAY_0, 14); + write(ad9154_reg::LMFC_DELAY_1, 14); write(ad9154_reg::LMFC_VAR_0, 4); // receive buffer delay write(ad9154_reg::LMFC_VAR_1, 4); write(ad9154_reg::SYNC_ERRWINDOW, 0); // +- 1/2 DAC clock From 34e89a37773ba15895977a0f50c7cd02dcfd479c Mon Sep 17 00:00:00 2001 From: Harry Ho Date: Thu, 9 Dec 2021 12:12:14 +0800 Subject: [PATCH 10/13] gth_ultrascale: fix TX/RX_CLK25_DIV for 125 MHz GTREFCLK0 --- artiq/gateware/drtio/transceiver/gth_ultrascale.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/artiq/gateware/drtio/transceiver/gth_ultrascale.py b/artiq/gateware/drtio/transceiver/gth_ultrascale.py index 0bf4e9e4c..e1ba2e6d5 100644 --- a/artiq/gateware/drtio/transceiver/gth_ultrascale.py +++ b/artiq/gateware/drtio/transceiver/gth_ultrascale.py @@ -312,7 +312,7 @@ class GTHSingle(Module): p_RX_BIAS_CFG0 =0b0000101010110100, p_RX_BUFFER_CFG =0b000000, p_RX_CAPFF_SARC_ENB =0b0, - p_RX_CLK25_DIV =6, + p_RX_CLK25_DIV =5, # Applicable to 125MHz RXPLLREFCLK_DIV1 = CPLL GTREFCLK0 p_RX_CLKMUX_EN =0b1, p_RX_CLK_SLIP_OVRD =0b00000, p_RX_CM_BUF_CFG =0b1010, @@ -411,7 +411,7 @@ class GTHSingle(Module): p_TXSYNC_MULTILANE =0 if mode == "single" else 1, p_TXSYNC_OVRD =0b0, p_TXSYNC_SKIP_DA =0b0, - p_TX_CLK25_DIV =6, + p_TX_CLK25_DIV =5, # Applicable to 125MHz TXPLLREFCLK_DIV1 = CPLL GTREFCLK0 p_TX_CLKMUX_EN =0b1, p_TX_DATA_WIDTH =dw, p_TX_DCD_CFG =0b000010, From 23f5796d671e61f533cd564e06b8d55456538139 Mon Sep 17 00:00:00 2001 From: Harry Ho Date: Thu, 9 Dec 2021 16:43:45 +0800 Subject: [PATCH 11/13] sayma: fix FTW for SyncDDS --- artiq/gateware/targets/sayma_amc.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/artiq/gateware/targets/sayma_amc.py b/artiq/gateware/targets/sayma_amc.py index 7e324c948..a29abaf21 100755 --- a/artiq/gateware/targets/sayma_amc.py +++ b/artiq/gateware/targets/sayma_amc.py @@ -240,7 +240,7 @@ class JDCGSyncDDS(Module, AutoCSR): self.sawgs = [] - ftw = round(2**len(self.coarse_ts)*9e6/600e6) + ftw = round(2**len(self.coarse_ts)*9e6/1000e6) parallelism = 8 mul_1 = Signal.like(self.coarse_ts) From 77c4d2f01316b823f66120293ee2dd1ed2a33c3e Mon Sep 17 00:00:00 2001 From: Harry Ho Date: Mon, 13 Dec 2021 10:37:50 +0800 Subject: [PATCH 12/13] siphaser: remove support for 150 MHz RTIO clock * Sayma AMC no longer uses 150 MHz RTIO clock after 1 GS/s upgrade. --- artiq/gateware/drtio/siphaser.py | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/artiq/gateware/drtio/siphaser.py b/artiq/gateware/drtio/siphaser.py index 81dacaed0..e3196714d 100644 --- a/artiq/gateware/drtio/siphaser.py +++ b/artiq/gateware/drtio/siphaser.py @@ -4,20 +4,20 @@ from migen.genlib.cdc import MultiReg, PulseSynchronizer from misoc.interconnect.csr import * -# This code assumes 125/62.5MHz reference clock and 125MHz or 150MHz RTIO +# This code assumes 125/62.5MHz reference clock and 125MHz RTIO # frequency. class SiPhaser7Series(Module, AutoCSR): def __init__(self, si5324_clkin, rx_synchronizer, - ref_clk=None, ref_div2=False, ultrascale=False, rtio_clk_freq=150e6): + ref_clk=None, ref_div2=False, ultrascale=False, rtio_clk_freq=125e6): self.switch_clocks = CSRStorage() self.phase_shift = CSR() self.phase_shift_done = CSRStatus(reset=1) self.error = CSR() - assert rtio_clk_freq in (125e6, 150e6) + assert rtio_clk_freq == 125e6 - # 125MHz/62.5MHz reference clock to 125MHz/150MHz. VCO @ 750MHz. + # 125MHz reference clock to 125MHz. VCO @ 750MHz. # Used to provide a startup clock to the transceiver through the Si, # we do not use the crystal reference so that the PFD (f3) frequency # can be high. @@ -43,8 +43,8 @@ class SiPhaser7Series(Module, AutoCSR): else: mmcm_freerun_output = mmcm_freerun_output_raw - # 125MHz/150MHz to 125MHz/150MHz with controllable phase shift, - # VCO @ 1000MHz/1200MHz. + # 125MHz to 125MHz with controllable phase shift, + # VCO @ 1000MHz. # Inserted between CDR and output to Si, used to correct # non-determinstic skew of Si5324. mmcm_ps_fb = Signal() From d3869c966e5118c2f68d37ab14d5d3f3221a3d7a Mon Sep 17 00:00:00 2001 From: Harry Ho Date: Mon, 13 Dec 2021 10:41:48 +0800 Subject: [PATCH 13/13] examples: fix RTIO clocks to 125 MHz --- artiq/examples/kasli_drtioswitching/device_db.py | 2 +- artiq/examples/kasli_sawgmaster/device_db.py | 4 ++-- artiq/examples/metlino_sayma_ttl/device_db.py | 2 +- artiq/examples/sayma_master/device_db.py | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/artiq/examples/kasli_drtioswitching/device_db.py b/artiq/examples/kasli_drtioswitching/device_db.py index 433eaf7bc..7c138bb54 100644 --- a/artiq/examples/kasli_drtioswitching/device_db.py +++ b/artiq/examples/kasli_drtioswitching/device_db.py @@ -5,7 +5,7 @@ device_db = { "type": "local", "module": "artiq.coredevice.core", "class": "Core", - "arguments": {"host": core_addr, "ref_period": 1/(8*150e6)} + "arguments": {"host": core_addr, "ref_period": 1/(8*125e6)} }, "core_log": { "type": "controller", diff --git a/artiq/examples/kasli_sawgmaster/device_db.py b/artiq/examples/kasli_sawgmaster/device_db.py index 4cba2bbd2..58f3e8376 100644 --- a/artiq/examples/kasli_sawgmaster/device_db.py +++ b/artiq/examples/kasli_sawgmaster/device_db.py @@ -5,7 +5,7 @@ device_db = { "type": "local", "module": "artiq.coredevice.core", "class": "Core", - "arguments": {"host": core_addr, "ref_period": 1/(8*150e6)} + "arguments": {"host": core_addr, "ref_period": 1/(8*125e6)} }, "core_log": { "type": "controller", @@ -69,7 +69,7 @@ device_db.update( "arguments": { "spi_device": "spi_urukul0", "io_update_device": "ttl_urukul0_io_update", - "refclk": 150e6, + "refclk": 125e6, "clk_sel": 2 } } diff --git a/artiq/examples/metlino_sayma_ttl/device_db.py b/artiq/examples/metlino_sayma_ttl/device_db.py index c8c3acb8e..d60addb5e 100644 --- a/artiq/examples/metlino_sayma_ttl/device_db.py +++ b/artiq/examples/metlino_sayma_ttl/device_db.py @@ -5,7 +5,7 @@ device_db = { "type": "local", "module": "artiq.coredevice.core", "class": "Core", - "arguments": {"host": core_addr, "ref_period": 1/(8*150e6)} + "arguments": {"host": core_addr, "ref_period": 1/(8*125e6)} }, "core_log": { "type": "controller", diff --git a/artiq/examples/sayma_master/device_db.py b/artiq/examples/sayma_master/device_db.py index 51eede704..07f8723f5 100644 --- a/artiq/examples/sayma_master/device_db.py +++ b/artiq/examples/sayma_master/device_db.py @@ -5,7 +5,7 @@ device_db = { "type": "local", "module": "artiq.coredevice.core", "class": "Core", - "arguments": {"host": core_addr, "ref_period": 1/(8*150e6)} + "arguments": {"host": core_addr, "ref_period": 1/(8*125e6)} }, "core_log": { "type": "controller",