mirror of
https://github.com/m-labs/artiq.git
synced 2024-12-19 00:16:29 +08:00
drtio: remove support for transceiver SMAs
Passive SFP cables do not require bitstream rebuilds and do not cause weird transceiver failures.
This commit is contained in:
parent
7b2eba9fbd
commit
94b0783897
@ -27,7 +27,7 @@ class Master(MiniSoC, AMPSoC):
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}
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}
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mem_map.update(MiniSoC.mem_map)
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mem_map.update(MiniSoC.mem_map)
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def __init__(self, cfg, medium, **kwargs):
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def __init__(self, cfg, **kwargs):
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MiniSoC.__init__(self,
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MiniSoC.__init__(self,
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cpu_type="or1k",
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cpu_type="or1k",
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sdram_controller_type="minicon",
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sdram_controller_type="minicon",
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@ -38,16 +38,9 @@ class Master(MiniSoC, AMPSoC):
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platform = self.platform
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platform = self.platform
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if medium == "sfp":
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self.comb += platform.request("sfp_tx_disable_n").eq(1)
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self.comb += platform.request("sfp_tx_disable_n").eq(1)
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tx_pads = platform.request("sfp_tx")
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tx_pads = platform.request("sfp_tx")
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rx_pads = platform.request("sfp_rx")
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rx_pads = platform.request("sfp_rx")
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elif medium == "sma":
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tx_pads = platform.request("user_sma_mgt_tx")
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rx_pads = platform.request("user_sma_mgt_rx")
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else:
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raise ValueError
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if cfg == "simple_gbe":
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if cfg == "simple_gbe":
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# GTX_1000BASE_BX10 Ethernet compatible, 62.5MHz RTIO clock
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# GTX_1000BASE_BX10 Ethernet compatible, 62.5MHz RTIO clock
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# simple TTLs
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# simple TTLs
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@ -110,12 +103,9 @@ def main():
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parser.add_argument("-c", "--config", default="simple_gbe",
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parser.add_argument("-c", "--config", default="simple_gbe",
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help="configuration: simple_gbe/sawg_3g "
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help="configuration: simple_gbe/sawg_3g "
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"(default: %(default)s)")
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"(default: %(default)s)")
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parser.add_argument("--medium", default="sfp",
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help="medium to use for transceiver link: sfp/sma "
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"(default: %(default)s)")
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args = parser.parse_args()
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args = parser.parse_args()
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soc = Master(args.config, args.medium, **soc_kc705_argdict(args))
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soc = Master(args.config, **soc_kc705_argdict(args))
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build_artiq_soc(soc, builder_argdict(args))
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build_artiq_soc(soc, builder_argdict(args))
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@ -125,7 +125,7 @@ class Satellite(BaseSoC):
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}
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}
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mem_map.update(BaseSoC.mem_map)
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mem_map.update(BaseSoC.mem_map)
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def __init__(self, cfg, medium, **kwargs):
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def __init__(self, cfg, **kwargs):
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BaseSoC.__init__(self,
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BaseSoC.__init__(self,
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cpu_type="or1k",
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cpu_type="or1k",
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sdram_controller_type="minicon",
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sdram_controller_type="minicon",
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@ -154,16 +154,9 @@ class Satellite(BaseSoC):
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sequencer.reset.eq(si5324_reset_clock.si5324_not_ready)
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sequencer.reset.eq(si5324_reset_clock.si5324_not_ready)
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]
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]
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if medium == "sfp":
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self.comb += platform.request("sfp_tx_disable_n").eq(1)
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self.comb += platform.request("sfp_tx_disable_n").eq(1)
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tx_pads = platform.request("sfp_tx")
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tx_pads = platform.request("sfp_tx")
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rx_pads = platform.request("sfp_rx")
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rx_pads = platform.request("sfp_rx")
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elif medium == "sma":
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tx_pads = platform.request("user_sma_mgt_tx")
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rx_pads = platform.request("user_sma_mgt_rx")
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else:
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raise ValueError
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if cfg == "simple_gbe":
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if cfg == "simple_gbe":
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# GTX_1000BASE_BX10 Ethernet compatible, 62.5MHz RTIO clock
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# GTX_1000BASE_BX10 Ethernet compatible, 62.5MHz RTIO clock
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# simple TTLs
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# simple TTLs
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@ -210,12 +203,9 @@ def main():
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parser.add_argument("-c", "--config", default="simple_gbe",
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parser.add_argument("-c", "--config", default="simple_gbe",
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help="configuration: simple_gbe/sawg_3g "
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help="configuration: simple_gbe/sawg_3g "
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"(default: %(default)s)")
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"(default: %(default)s)")
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parser.add_argument("--medium", default="sfp",
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help="medium to use for transceiver link: sfp/sma "
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"(default: %(default)s)")
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args = parser.parse_args()
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args = parser.parse_args()
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soc = Satellite(args.config, args.medium, **soc_kc705_argdict(args))
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soc = Satellite(args.config, **soc_kc705_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.add_software_package("liballoc")
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builder.add_software_package("liballoc")
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builder.add_software_package("satman", os.path.join(artiq_dir, "firmware", "satman"))
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builder.add_software_package("satman", os.path.join(artiq_dir, "firmware", "satman"))
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