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fir: different adder layout

This commit is contained in:
Robert Jördens 2016-12-14 00:01:45 +01:00
parent 61abd994e9
commit 93076b8efa
1 changed files with 5 additions and 4 deletions
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9
artiq/gateware/dsp/fir.py
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@ -102,18 +102,19 @@ class ParallelFIR(Module):
for j in range(p): for j in range(p):
# Make products # Make products
o = [] o = Signal((width + shift, True))
for i, c in enumerate(coefficients): for i, c in enumerate(coefficients):
# simplify for halfband and symmetric filters # simplify for halfband and symmetric filters
if c == 0 or c in coefficients[i + 1:]: if c == 0 or c in coefficients[i + 1:]:
continue continue
m = Signal((width + shift, True)) m = Signal.like(o)
self.sync += m.eq(c*reduce(add, [ self.sync += m.eq(c*reduce(add, [
xj for xj, cj in zip(x[-1 - j::-1], coefficients) if cj == c xj for xj, cj in zip(x[-1 - j::-1], coefficients) if cj == c
])) ]))
o.append(m) o0, o = o, Signal.like(o)
self.comb += o.eq(o0 + m)
# Make sum # Make sum
self.sync += self.o[j].eq(reduce(add, o) >> shift) self.sync += self.o[j].eq(o >> shift)
def halfgen4_cascade(rate, width, order=None): def halfgen4_cascade(rate, width, order=None):