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devices/dds_core: support realtime FUD and zero-length pulse collapsing
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@ -1,35 +1,44 @@
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from artiq.language.core import *
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from artiq.language.units import *
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from artiq.devices import rtio_core
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class DDS(AutoContext):
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parameters = "dds_sysclk reg_channel rtio_channel"
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def build(self):
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self._previous_frequency = 0*MHz
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self.previous_frequency = 0*MHz
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self.sw = rtio_core.RTIOOut(self, channel=self.rtio_channel)
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kernel_attr = "_previous_frequency"
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@kernel
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def _set_frequency(self, frequency):
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if self._previous_frequency != frequency:
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syscall("rtio_sync", self.rtio_channel) # wait until output is off
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syscall("dds_program", self.reg_channel,
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int(2**32*frequency/self.dds_sysclk))
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self._previous_frequency = frequency
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@kernel
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def pulse(self, frequency, duration):
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self._set_frequency(frequency)
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syscall("rtio_set", now(), self.rtio_channel, 1)
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delay(duration)
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syscall("rtio_set", now(), self.rtio_channel, 0)
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kernel_attr = "previous_frequency previous_timestamp"
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@kernel
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def on(self, frequency):
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self._set_frequency(frequency)
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syscall("rtio_set", now(), self.rtio_channel, 1)
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if self.previous_frequency != frequency:
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if self.sw.previous_timestamp != now():
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self.sw.sync()
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if self.sw.previous_value:
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# Channel is already on.
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# Precise timing of frequency change is required.
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fud_time = now()
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else:
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# Channel is off.
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# Use soft timing on FUD to prevent conflicts when
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# reprogramming several channels that need to be turned on at
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# the same time.
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fud_time = -1
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syscall("dds_program", self.reg_channel,
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int(2**32*frequency/self.dds_sysclk),
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fud_time)
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self.previous_frequency = frequency
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self.sw.on()
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@kernel
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def off(self):
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syscall("rtio_set", now(), self.rtio_channel, 0)
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self.sw.off()
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@kernel
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def pulse(self, frequency, duration):
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self.on(frequency)
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delay(duration)
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self.off()
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