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https://github.com/m-labs/artiq.git
synced 2024-12-28 20:53:35 +08:00
firmware: fix DMA trace alignment and flush caches.
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30ac42de3f
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@ -320,9 +320,10 @@ extern fn dma_playback(timestamp: i64, name: CSlice<u8>) {
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let succeeded = recv!(&DmaPlaybackReply(data) => unsafe {
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match data {
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Some(bytes) => {
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// Here, we take advantage of the fact that DmaPlaybackReply always refers
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// to an entire heap allocation, which is 4-byte-aligned.
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csr::rtio_dma::base_address_write(bytes.as_ptr() as u64);
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let ptr = bytes.as_ptr() as usize;
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assert!(ptr % 64 == 0);
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csr::rtio_dma::base_address_write(ptr as u64);
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csr::rtio_dma::time_offset_write(timestamp as u64);
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rtio_arb_dma();
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@ -4,9 +4,12 @@ use std::string::String;
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use std::btree_map::BTreeMap;
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use std::io::Write;
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const ALIGNMENT: usize = 64;
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#[derive(Debug)]
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struct Entry {
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data: Vec<u8>
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data: Vec<u8>,
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padding: usize
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}
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#[derive(Debug)]
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@ -24,7 +27,7 @@ impl Manager {
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}
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pub fn record_start(&mut self) {
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self.recording.clear();
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self.recording = Vec::new();
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}
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pub fn record_append(&mut self, timestamp: u64, channel: u32,
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@ -63,12 +66,23 @@ impl Manager {
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let mut recorded = Vec::new();
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mem::swap(&mut self.recording, &mut recorded);
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recorded.push(0);
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recorded.shrink_to_fit();
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let data_len = recorded.len();
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info!("recorded DMA data: {:?}", recorded);
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// Realign.
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recorded.reserve(ALIGNMENT - 1);
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let padding = ALIGNMENT - recorded.as_ptr() as usize % ALIGNMENT;
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let padding = if padding == ALIGNMENT { 0 } else { padding };
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for _ in 0..padding {
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// Vec guarantees that this will not reallocate
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recorded.push(0)
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}
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for i in 1..data_len + 1 {
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recorded[data_len + padding - i] = recorded[data_len - i]
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}
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self.entries.insert(String::from(name), Entry {
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data: recorded
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data: recorded,
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padding: padding,
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});
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}
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@ -77,6 +91,8 @@ impl Manager {
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}
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pub fn with_trace<F: FnOnce(Option<&[u8]>) -> R, R>(&self, name: &str, f: F) -> R {
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f(self.entries.get(name).map(|entry| &entry.data[..]))
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f(self.entries
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.get(name)
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.map(|entry| &entry.data[entry.padding..]))
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}
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}
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@ -410,6 +410,8 @@ fn process_kern_message(io: &Io, mut stream: Option<&mut TcpStream>,
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}
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&kern::DmaRecordStop(name) => {
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session.congress.dma_manager.record_stop(name);
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board::cache::flush_cpu_dcache();
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board::cache::flush_l2_cache();
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kern_acknowledge()
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}
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&kern::DmaEraseRequest(name) => {
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