mirror of https://github.com/m-labs/artiq.git
sayma_rtm: expose HMC SPI bus
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dbc12540da
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@ -8,6 +8,7 @@ from migen.build.platforms.sinara import sayma_rtm
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from misoc.interconnect import wishbone, stream
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from misoc.interconnect import wishbone, stream
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from misoc.interconnect.csr import *
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from misoc.interconnect.csr import *
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from misoc.cores import spi
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from misoc.integration.wb_slaves import WishboneSlaveManager
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from misoc.integration.wb_slaves import WishboneSlaveManager
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from misoc.integration.cpu_interface import get_csr_csv
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from misoc.integration.cpu_interface import get_csr_csv
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@ -80,6 +81,10 @@ class SaymaRTM(Module):
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self.submodules.rtm_identifier = RTMIdentifier()
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self.submodules.rtm_identifier = RTMIdentifier()
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csr_devices.append("rtm_identifier")
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csr_devices.append("rtm_identifier")
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self.submodules.converter_spi = spi.SPIMaster(platform.request("hmc_spi"))
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csr_devices.append("converter_spi")
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self.comb += platform.request("hmc7043_reset").eq(0)
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# TODO: push all those serwb bits into library modules
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# TODO: push all those serwb bits into library modules
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# maybe keep only 3 user-visible modules: serwb PLL, serwb PHY, and serwb core
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# maybe keep only 3 user-visible modules: serwb PLL, serwb PHY, and serwb core
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# TODO: after this is done, stop exposing internal modules in serwb/__init__.py
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# TODO: after this is done, stop exposing internal modules in serwb/__init__.py
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