From 916197c4d78ac1ebd58d7ffe2c16e0b1d7647797 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Wed, 7 Mar 2018 11:15:44 +0800 Subject: [PATCH] siphaser: cleanup --- artiq/firmware/libboard_artiq/si5324.rs | 145 +++++++++--------- artiq/firmware/satman/main.rs | 6 +- .../drtio/{si_phaser.py => siphaser.py} | 0 artiq/gateware/targets/kasli.py | 6 +- artiq/gateware/targets/sayma_amc.py | 8 +- 5 files changed, 83 insertions(+), 82 deletions(-) rename artiq/gateware/drtio/{si_phaser.py => siphaser.py} (100%) diff --git a/artiq/firmware/libboard_artiq/si5324.rs b/artiq/firmware/libboard_artiq/si5324.rs index 9b93eae96..8cd8d94d8 100644 --- a/artiq/firmware/libboard_artiq/si5324.rs +++ b/artiq/firmware/libboard_artiq/si5324.rs @@ -1,6 +1,6 @@ use core::result; use board::clock; -#[cfg(any(not(si5324_soft_reset), has_si_phaser))] +#[cfg(not(si5324_soft_reset))] use board::csr; use i2c; @@ -266,90 +266,91 @@ pub fn select_input(input: Input) -> Result<()> { Ok(()) } -#[cfg(has_si_phaser)] -pub fn select_recovered_clock(rc: bool) -> Result<()> { - write(3, (read(3)? & 0xdf) | (1 << 5))?; // DHOLD=1 - unsafe { - csr::si_phaser::switch_clocks_write(if rc { 1 } else { 0 }); - } - write(3, (read(3)? & 0xdf) | (0 << 5))?; // DHOLD=0 - monitor_lock()?; - Ok(()) -} +#[cfg(has_siphaser)] +pub mod siphaser { + use super::*; + use board::csr; + use board::clock; -#[cfg(has_si_phaser)] -fn phase_shift(direction: u8) { - unsafe { - csr::si_phaser::phase_shift_write(direction); - while csr::si_phaser::phase_shift_done_read() == 0 {} - } - // wait for the Si5324 loop to stabilize - clock::spin_us(500); -} - -#[cfg(has_si_phaser)] -fn get_phaser_sample() -> bool { - let mut sample = true; - for _ in 0..32 { - if unsafe { csr::si_phaser::sample_result_read() } == 0 { - sample = false; + pub fn select_recovered_clock(rc: bool) -> Result<()> { + write(3, (read(3)? & 0xdf) | (1 << 5))?; // DHOLD=1 + unsafe { + csr::siphaser::switch_clocks_write(if rc { 1 } else { 0 }); } + write(3, (read(3)? & 0xdf) | (0 << 5))?; // DHOLD=0 + monitor_lock()?; + Ok(()) } - sample -} -#[cfg(has_si_phaser)] -const PS_MARGIN: u32 = 28; + fn phase_shift(direction: u8) { + unsafe { + csr::siphaser::phase_shift_write(direction); + while csr::siphaser::phase_shift_done_read() == 0 {} + } + // wait for the Si5324 loop to stabilize + clock::spin_us(500); + } -#[cfg(has_si_phaser)] -fn get_stable_phaser_sample() -> (bool, u32) { - let mut nshifts: u32 = 0; - loop { - let s1 = get_phaser_sample(); - for _ in 0..PS_MARGIN { - phase_shift(1); - } - let s2 = get_phaser_sample(); - for _ in 0..PS_MARGIN { - phase_shift(1); - } - let s3 = get_phaser_sample(); - nshifts += 2*PS_MARGIN; - if s1 == s2 && s2 == s3 { - for _ in 0..PS_MARGIN { - phase_shift(0); + fn get_phaser_sample() -> bool { + let mut sample = true; + for _ in 0..32 { + if unsafe { csr::siphaser::sample_result_read() } == 0 { + sample = false; + } + } + sample + } + + const PS_MARGIN: u32 = 28; + + fn get_stable_phaser_sample() -> (bool, u32) { + let mut nshifts: u32 = 0; + loop { + let s1 = get_phaser_sample(); + for _ in 0..PS_MARGIN { + phase_shift(1); + } + let s2 = get_phaser_sample(); + for _ in 0..PS_MARGIN { + phase_shift(1); + } + let s3 = get_phaser_sample(); + nshifts += 2*PS_MARGIN; + if s1 == s2 && s2 == s3 { + for _ in 0..PS_MARGIN { + phase_shift(0); + } + nshifts -= PS_MARGIN; + return (s2, nshifts); } - nshifts -= PS_MARGIN; - return (s2, nshifts); } } -} -#[cfg(has_si_phaser)] -pub fn calibrate_skew(skew: u16) -> Result<()> { - // Get into a 0 region - let (s1, mut nshifts) = get_stable_phaser_sample(); - if s1 { - while get_phaser_sample() { + pub fn calibrate_skew(skew: u16) -> Result<()> { + // Get into a 0 region + let (s1, mut nshifts) = get_stable_phaser_sample(); + if s1 { + while get_phaser_sample() { + phase_shift(1); + nshifts += 1; + } + for _ in 0..PS_MARGIN { + phase_shift(1); + } + nshifts += PS_MARGIN; + } + + // Get to the 0->1 transition + while !get_phaser_sample() { phase_shift(1); nshifts += 1; } - for _ in 0..PS_MARGIN { + info!("nshifts to 0->1 siphaser transition: {} ({}deg)", nshifts, nshifts*360/(56*8)); + + // Apply specified skew referenced to that transition + for _ in 0..skew { phase_shift(1); } - nshifts += PS_MARGIN; + Ok(()) } - - // Get to the 0->1 transition - while !get_phaser_sample() { - phase_shift(1); - nshifts += 1; - } - info!("nshifts to 0->1 siphaser transition: {} ({}deg)", nshifts, nshifts*360/(56*8)); - - // Apply specified skew referenced to that transition - for _ in 0..skew { - phase_shift(1); - } - Ok(()) } diff --git a/artiq/firmware/satman/main.rs b/artiq/firmware/satman/main.rs index 19f0d2517..c00c5b484 100644 --- a/artiq/firmware/satman/main.rs +++ b/artiq/firmware/satman/main.rs @@ -235,8 +235,8 @@ fn startup() { process_errors(); } info!("link is up, switching to recovered clock"); - si5324::select_recovered_clock(true).expect("failed to switch clocks"); - si5324::calibrate_skew(32).expect("failed to calibrate skew"); + si5324::siphaser::select_recovered_clock(true).expect("failed to switch clocks"); + si5324::siphaser::calibrate_skew(32).expect("failed to calibrate skew"); drtio_reset(false); drtio_reset_phy(false); while drtio_link_rx_up() { @@ -246,7 +246,7 @@ fn startup() { drtio_reset_phy(true); drtio_reset(true); info!("link is down, switching to local crystal clock"); - si5324::select_recovered_clock(false).expect("failed to switch clocks"); + si5324::siphaser::select_recovered_clock(false).expect("failed to switch clocks"); } } diff --git a/artiq/gateware/drtio/si_phaser.py b/artiq/gateware/drtio/siphaser.py similarity index 100% rename from artiq/gateware/drtio/si_phaser.py rename to artiq/gateware/drtio/siphaser.py diff --git a/artiq/gateware/targets/kasli.py b/artiq/gateware/targets/kasli.py index 77791cfed..05542e817 100755 --- a/artiq/gateware/targets/kasli.py +++ b/artiq/gateware/targets/kasli.py @@ -21,7 +21,7 @@ from artiq.gateware.amp import AMPSoC from artiq.gateware import rtio from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series, spi2 from artiq.gateware.drtio.transceiver import gtp_7series -from artiq.gateware.drtio.si_phaser import SiPhaser7Series +from artiq.gateware.drtio.siphaser import SiPhaser7Series from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer from artiq.gateware.drtio import DRTIOMaster, DRTIOSatellite from artiq.build_soc import build_artiq_soc @@ -574,11 +574,11 @@ class Satellite(BaseSoC): self.add_memory_group("drtio_aux", ["drtio0_aux"]) self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6) - self.submodules.si_phaser = SiPhaser7Series( + self.submodules.siphaser = SiPhaser7Series( si5324_clkin=platform.request("si5324_clkin"), si5324_clkout_fabric=platform.request("si5324_clkout_fabric") ) - self.csr_devices.append("si_phaser") + self.csr_devices.append("siphaser") i2c = self.platform.request("i2c") self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda]) self.csr_devices.append("i2c") diff --git a/artiq/gateware/targets/sayma_amc.py b/artiq/gateware/targets/sayma_amc.py index ae650216f..6e909f2db 100755 --- a/artiq/gateware/targets/sayma_amc.py +++ b/artiq/gateware/targets/sayma_amc.py @@ -33,7 +33,7 @@ from artiq.gateware import remote_csr from artiq.gateware import rtio from artiq.gateware.rtio.phy import ttl_simple, sawg from artiq.gateware.drtio.transceiver import gth_ultrascale -from artiq.gateware.drtio.si_phaser import SiPhaser7Series +from artiq.gateware.drtio.siphaser import SiPhaser7Series from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer from artiq.gateware.drtio import DRTIOMaster, DRTIOSatellite from artiq.build_soc import build_artiq_soc @@ -433,13 +433,13 @@ class Satellite(BaseSoC): self.add_memory_group("drtio_aux", ["drtio0_aux"]) self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6) - self.submodules.si_phaser = SiPhaser7Series( + self.submodules.siphaser = SiPhaser7Series( si5324_clkin=platform.request("si5324_clkin"), si5324_clkout_fabric=platform.request("si5324_clkout_fabric") ) platform.add_platform_command("set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {mmcm_ps}]", - mmcm_ps=self.si_phaser.mmcm_ps_output) - self.csr_devices.append("si_phaser") + mmcm_ps=self.siphaser.mmcm_ps_output) + self.csr_devices.append("siphaser") self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n) self.csr_devices.append("si5324_rst_n") i2c = self.platform.request("i2c")