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rtio: expose coarse timestamp in RTIO and DRTIO satellite cores

This commit is contained in:
Sebastien Bourdeauducq 2018-06-20 17:39:43 +08:00
parent 5272c11704
commit 9142a5ab8a
2 changed files with 2 additions and 0 deletions
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1
artiq/gateware/drtio/core.py
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@ -90,6 +90,7 @@ class DRTIOSatellite(Module):
coarse_ts.eq(coarse_ts + 1) coarse_ts.eq(coarse_ts + 1)
) )
self.comb += self.rt_packet.cri.counter.eq(coarse_ts << fine_ts_width) self.comb += self.rt_packet.cri.counter.eq(coarse_ts << fine_ts_width)
self.coarse_ts = coarse_ts
self.submodules.outputs = ClockDomainsRenamer("rio")( self.submodules.outputs = ClockDomainsRenamer("rio")(
SED(channels, fine_ts_width, "sync", SED(channels, fine_ts_width, "sync",

1
artiq/gateware/rtio/core.py
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@ -73,6 +73,7 @@ class Core(Module, AutoCSR):
coarse_ts_cdc.i.eq(coarse_ts), coarse_ts_cdc.i.eq(coarse_ts),
self.cri.counter.eq(coarse_ts_cdc.o << glbl_fine_ts_width) self.cri.counter.eq(coarse_ts_cdc.o << glbl_fine_ts_width)
] ]
self.coarse_ts = coarse_ts
# Outputs/Inputs # Outputs/Inputs
quash_channels = [n for n, c in enumerate(channels) if isinstance(c, LogChannel)] quash_channels = [n for n, c in enumerate(channels) if isinstance(c, LogChannel)]