M-Labs
/
artiq
mirror of https://github.com/m-labs/artiq.git
2
0
Fork 2
Code Issues Projects Releases Wiki Activity

gateware/dds/monitor: support onehot selection, strip reset

This commit is contained in:
Sebastien Bourdeauducq 2015-08-27 15:54:01 +08:00
parent 0fe0f4d433
commit 90ce54d8d5
2 changed files with 18 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

28
artiq/gateware/rtio/phy/dds.py
View File

@ -5,7 +5,7 @@ from artiq.gateware.rtio.phy.wishbone import RT2WB
class _AD9xxx(Module): class _AD9xxx(Module):
def __init__(self, ftw_base, pads, nchannels, **kwargs): def __init__(self, ftw_base, pads, nchannels, onehot=False, **kwargs):
self.submodules._ll = RenameClockDomains( self.submodules._ll = RenameClockDomains(
ad9xxx.AD9xxx(pads, **kwargs), "rio") ad9xxx.AD9xxx(pads, **kwargs), "rio")
self.submodules._rt2wb = RT2WB(flen(pads.a)+1, self._ll.bus) self.submodules._rt2wb = RT2WB(flen(pads.a)+1, self._ll.bus)
@ -21,23 +21,29 @@ class _AD9xxx(Module):
current_address.eq(self.rtlink.o.address), current_address.eq(self.rtlink.o.address),
current_data.eq(self.rtlink.o.data)) current_data.eq(self.rtlink.o.data))
# keep track of the currently selected channel # keep track of the currently selected channel(s)
current_channel = Signal(max=nchannels) current_sel = Signal(flen(current_data)-1)
self.sync.rio += If(current_address == 2**flen(pads.a) + 1, self.sync.rio += If(current_address == 2**flen(pads.a) + 1,
current_channel.eq(current_data)) current_sel.eq(current_data[1:])) # strip reset
def selected(c):
if onehot:
return current_sel[c]
else:
return current_sel == c
# keep track of frequency tuning words, before they are FUDed # keep track of frequency tuning words, before they are FUDed
ftws = [Signal(32) for i in range(nchannels)] ftws = [Signal(32) for i in range(nchannels)]
for c, ftw in enumerate(ftws): for c, ftw in enumerate(ftws):
if flen(pads.d) == 8: if flen(pads.d) == 8:
self.sync.rio += \ self.sync.rio += \
If(current_channel == c, [ If(selected(c), [
If(current_address == ftw_base+i, If(current_address == ftw_base+i,
ftw[i*8:(i+1)*8].eq(current_data)) ftw[i*8:(i+1)*8].eq(current_data))
for i in range(4)]) for i in range(4)])
elif flen(pads.d) == 16: elif flen(pads.d) == 16:
self.sync.rio += \ self.sync.rio += \
If(current_channel == c, [ If(selected(c), [
If(current_address == ftw_base+2*i, If(current_address == ftw_base+2*i,
ftw[i*16:(i+1)*16].eq(current_data)) ftw[i*16:(i+1)*16].eq(current_data))
for i in range(2)]) for i in range(2)])
@ -46,15 +52,15 @@ class _AD9xxx(Module):
# FTW to probe on FUD # FTW to probe on FUD
self.sync.rio += If(current_address == 2**flen(pads.a), [ self.sync.rio += If(current_address == 2**flen(pads.a), [
If(current_channel == c, probe.eq(ftw)) If(selected(c), probe.eq(ftw))
for c, (probe, ftw) in enumerate(zip(self.probes, ftws))]) for c, (probe, ftw) in enumerate(zip(self.probes, ftws))])
class AD9858(_AD9xxx): class AD9858(_AD9xxx):
def __init__(self, pads, nchannels, **kwargs): def __init__(self, *args, **kwargs):
_AD9xxx.__init__(self, 0x0a, pads, nchannels, **kwargs) _AD9xxx.__init__(self, 0x0a, *args, **kwargs)
class AD9914(_AD9xxx): class AD9914(_AD9xxx):
def __init__(self, pads, nchannels, **kwargs): def __init__(self, *args, **kwargs):
_AD9xxx.__init__(self, 0x2d, pads, nchannels, **kwargs) _AD9xxx.__init__(self, 0x2d, *args, **kwargs)

2
soc/targets/artiq_kc705.py
View File

@ -206,7 +206,7 @@ class NIST_QC2(_NIST_QCx):
self.add_constant("DDS_CHANNEL_COUNT", 11) self.add_constant("DDS_CHANNEL_COUNT", 11)
self.add_constant("DDS_AD9914") self.add_constant("DDS_AD9914")
self.add_constant("DDS_ONEHOT_SEL") self.add_constant("DDS_ONEHOT_SEL")
phy = dds.AD9914(platform.request("dds"), 11) phy = dds.AD9914(platform.request("dds"), 11, onehot=True)
self.submodules += phy self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, rtio_channels.append(rtio.Channel.from_phy(phy,
ofifo_depth=512, ofifo_depth=512,