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satellite: add dma to gateware

pull/2055/head
mwojcik 2023-02-23 16:00:10 +08:00 committed by Sébastien Bourdeauducq
parent d0437f5672
commit 90a6fe1c35
2 changed files with 6 additions and 2 deletions
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4
artiq/gateware/targets/kasli.py
View File

@ -567,8 +567,10 @@ class SatelliteBase(BaseSoC):
self.submodules.local_io = SyncRTIO(self.rtio_tsc, rtio_channels, lane_count=sed_lanes)
self.comb += self.drtiosat.async_errors.eq(self.local_io.async_errors)
self.submodules.rtio_dma = rtio.DMA(self.get_native_sdram_if(), self.cpu_dw)
self.csr_devices.append("rtio_dma")
self.submodules.cri_con = rtio.CRIInterconnectShared(
[self.drtiosat.cri],
[self.drtiosat.cri, self.rtio_dma.cri],
[self.local_io.cri] + self.drtio_cri,
enable_routing=True)
self.csr_devices.append("cri_con")

4
artiq/gateware/targets/kc705.py
View File

@ -451,8 +451,10 @@ class _SatelliteBase(BaseSoC):
self.submodules.local_io = SyncRTIO(self.rtio_tsc, rtio_channels)
self.comb += self.drtiosat.async_errors.eq(self.local_io.async_errors)
self.submodules.rtio_dma = rtio.DMA(self.get_native_sdram_if(), self.cpu_dw)
self.csr_devices.append("rtio_dma")
self.submodules.cri_con = rtio.CRIInterconnectShared(
[self.drtiosat.cri],
[self.drtiosat.cri, self.rtio_dma.cri],
[self.local_io.cri] + self.drtio_cri,
enable_routing=True)
self.csr_devices.append("cri_con")