mirror of https://github.com/m-labs/artiq.git
ad9912: use pll doubler for refclk <11mhz
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@ -44,7 +44,11 @@ class AD9912:
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self.pll_en = pll_en
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self.pll_n = pll_n
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if pll_en:
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sysclk = self.cpld.refclk / [1, 1, 2, 4][self.cpld.clk_div] * pll_n
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refclk = self.cpld.refclk
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if refclk < 11e6:
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# use SYSCLK PLL Doubler
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refclk = refclk * 2
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sysclk = refclk / [1, 1, 2, 4][self.cpld.clk_div] * pll_n
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else:
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sysclk = self.cpld.refclk
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assert sysclk <= 1e9
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@ -115,7 +119,11 @@ class AD9912:
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self.write(AD9912_N_DIV, self.pll_n // 2 - 2, length=1)
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self.cpld.io_update.pulse(2 * us)
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# I_cp = 375 µA, VCO high range
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self.write(AD9912_PLLCFG, 0b00000101, length=1)
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if self.cpld.refclk < 11e6:
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# enable SYSCLK PLL Doubler
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self.write(AD9912_PLLCFG, 0b00001101, length=1)
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else:
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self.write(AD9912_PLLCFG, 0b00000101, length=1)
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self.cpld.io_update.pulse(2 * us)
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delay(1 * ms)
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