From 90424268725a3cda3f34de5aa29670f308f64ce3 Mon Sep 17 00:00:00 2001 From: mwojcik Date: Tue, 10 Jan 2023 17:17:39 +0800 Subject: [PATCH] echo test: add two more yields --- artiq/gateware/test/drtio/test_full_stack.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/artiq/gateware/test/drtio/test_full_stack.py b/artiq/gateware/test/drtio/test_full_stack.py index 61fb43d2a..e55bb536a 100644 --- a/artiq/gateware/test/drtio/test_full_stack.py +++ b/artiq/gateware/test/drtio/test_full_stack.py @@ -303,7 +303,7 @@ class TestFullStack(unittest.TestCase): yield yield dut.master.rt_packet.echo_stb.eq(0) - for i in range(15): + for i in range(17): yield self.assertEqual((yield dut.master.rt_packet.packet_cnt_tx), 1)