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shiftreg: fix get method

This commit is contained in:
Sebastien Bourdeauducq 2019-12-21 14:17:22 +08:00
parent 0e847c07da
commit 902db1d95a
1 changed files with 2 additions and 1 deletions
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3
artiq/coredevice/shiftreg.py
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@ -43,7 +43,8 @@ class ShiftReg:
data = 0 data = 0
for i in range(self.n): for i in range(self.n):
data <<= 1 data <<= 1
if self.ser_in.sample_input(): self.ser_in.sample_input()
if self.ser_in.sample_get():
data |= 1 data |= 1
delay(self.dt) delay(self.dt)
self.clk.on() self.clk.on()