shiftreg: fix get method

2019-12-21 14:17:22 +08:00 · 2019-12-21 14:17:22 +08:00 · 902db1d95a
parent 0e847c07da
commit 902db1d95a
1 changed files with 2 additions and 1 deletions
--- a/artiq/coredevice/shiftreg.py
+++ b/artiq/coredevice/shiftreg.py
@ -43,7 +43,8 @@ class ShiftReg:
        data = 0
        for i in range(self.n):
            data <<= 1
-            if self.ser_in.sample_input():
+            self.ser_in.sample_input()
+            if self.ser_in.sample_get():
                data |= 1
            delay(self.dt)
            self.clk.on()