sayma_rtm: add UART loopback to easily know if rtm fpga is alive

2018-01-20 06:02:05 +01:00 · 2018-01-20 06:02:05 +01:00 · 8fe463d4a0
parent 74ce7319d3
commit 8fe463d4a0
1 changed files with 4 additions and 0 deletions
--- a/artiq/gateware/targets/sayma_rtm.py
+++ b/artiq/gateware/targets/sayma_rtm.py
@ -93,6 +93,10 @@ class SaymaRTM(Module):
            platform.request("dac_clk_src_sel")))
        csr_devices.append("clock_mux")

+        # UART loopback
+        serial = platform.request(serial)
+        self.comb += serial.tx.eq(serial.rx)
+
        # Allaki: enable RF output, GPIO access to attenuator
        self.comb += [
            platform.request("allaki0_rfsw0").eq(1),