From 8f747fa20917f08e57b70ee7d63e9ccaa8d3f28e Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Mon, 12 Dec 2016 17:39:14 +0800 Subject: [PATCH] drtio: clear underflow and sequence error on reset --- artiq/gateware/drtio/rt_controller.py | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/artiq/gateware/drtio/rt_controller.py b/artiq/gateware/drtio/rt_controller.py index ce0066e49..6f9518240 100644 --- a/artiq/gateware/drtio/rt_controller.py +++ b/artiq/gateware/drtio/rt_controller.py @@ -105,6 +105,10 @@ class RTController(Module): If(self.cri.cmd == cri.commands["o_sequence_error_reset"], status_sequence_error.eq(0)), If(underflow_set, status_underflow.eq(1)), If(sequence_error_set, status_sequence_error.eq(1)), + If(self.csrs.reset.re, + status_underflow.eq(0), + status_sequence_error.eq(0) + ) ] signal_fifo_space_timeout = Signal()