mirror of https://github.com/m-labs/artiq.git
firmware: fix sayma_amc_standalone build with sawg.
This commit is contained in:
parent
4ea801b2ea
commit
8f33061a6d
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@ -1,5 +1,4 @@
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use csr;
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use board::{csr, clock};
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use clock;
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use ad9154_reg;
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use ad9154_reg;
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fn spi_setup(dacno: u8) {
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fn spi_setup(dacno: u8) {
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@ -11,7 +11,7 @@
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*/
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*/
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mod clock_mux {
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mod clock_mux {
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use csr;
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use board::csr;
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const CLK_SRC_EXT_SEL : u8 = 1 << 0;
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const CLK_SRC_EXT_SEL : u8 = 1 << 0;
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const REF_CLK_SRC_SEL : u8 = 1 << 1;
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const REF_CLK_SRC_SEL : u8 = 1 << 1;
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@ -28,8 +28,7 @@ mod clock_mux {
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}
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}
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mod hmc830 {
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mod hmc830 {
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use clock;
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use board::{csr, clock};
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use csr;
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const HMC830_WRITES: [(u8, u32); 16] = [
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const HMC830_WRITES: [(u8, u32); 16] = [
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(0x0, 0x20),
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(0x0, 0x20),
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@ -117,7 +116,7 @@ mod hmc830 {
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}
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}
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mod hmc7043 {
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mod hmc7043 {
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use csr;
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use board::csr;
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include!(concat!(env!("OUT_DIR"), "/hmc7043_writes.rs"));
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include!(concat!(env!("OUT_DIR"), "/hmc7043_writes.rs"));
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@ -1,4 +1,4 @@
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use csr;
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use board::csr;
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pub fn wait_init() {
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pub fn wait_init() {
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info!("waiting for AMC/RTM serwb bridge to be ready...");
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info!("waiting for AMC/RTM serwb bridge to be ready...");
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@ -1,66 +1,67 @@
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#[cfg(has_converter_spi)]
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#[cfg(has_converter_spi)]
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use csr;
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mod imp {
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use board::csr;
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#[cfg(has_converter_spi)]
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pub fn set_config(busno: u8, flags: u8, write_div: u8, read_div: u8) -> Result<(), ()> {
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pub fn set_config(busno: u8, flags: u8, write_div: u8, read_div: u8) -> Result<(), ()> {
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if busno != 0 {
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if busno != 0 {
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return Err(())
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return Err(())
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}
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unsafe {
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csr::converter_spi::offline_write(1);
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csr::converter_spi::cs_polarity_write(flags >> 3 & 1);
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csr::converter_spi::clk_polarity_write(flags >> 4 & 1);
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csr::converter_spi::clk_phase_write(flags >> 5 & 1);
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csr::converter_spi::lsb_first_write(flags >> 6 & 1);
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csr::converter_spi::half_duplex_write(flags >> 7 & 1);
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csr::converter_spi::clk_div_write_write(write_div);
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csr::converter_spi::clk_div_read_write(read_div);
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csr::converter_spi::offline_write(0);
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}
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Ok(())
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}
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}
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unsafe {
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csr::converter_spi::offline_write(1);
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csr::converter_spi::cs_polarity_write(flags >> 3 & 1);
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csr::converter_spi::clk_polarity_write(flags >> 4 & 1);
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csr::converter_spi::clk_phase_write(flags >> 5 & 1);
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csr::converter_spi::lsb_first_write(flags >> 6 & 1);
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csr::converter_spi::half_duplex_write(flags >> 7 & 1);
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csr::converter_spi::clk_div_write_write(write_div);
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csr::converter_spi::clk_div_read_write(read_div);
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csr::converter_spi::offline_write(0);
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}
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Ok(())
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}
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#[cfg(has_converter_spi)]
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pub fn set_xfer(busno: u8, chip_select: u16, write_length: u8, read_length: u8)
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pub fn set_xfer(busno: u8, chip_select: u16, write_length: u8, read_length: u8) -> Result<(), ()> {
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-> Result<(), ()> {
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if busno != 0 {
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if busno != 0 {
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return Err(())
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return Err(())
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}
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unsafe {
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csr::converter_spi::cs_write(chip_select as _);
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csr::converter_spi::xfer_len_write_write(write_length);
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csr::converter_spi::xfer_len_read_write(read_length);
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}
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Ok(())
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}
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}
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unsafe {
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csr::converter_spi::cs_write(chip_select as _);
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csr::converter_spi::xfer_len_write_write(write_length);
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csr::converter_spi::xfer_len_read_write(read_length);
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}
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Ok(())
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}
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#[cfg(has_converter_spi)]
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pub fn write(busno: u8, data: u32) -> Result<(), ()> {
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pub fn write(busno: u8, data: u32) -> Result<(), ()> {
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if busno != 0 {
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if busno != 0 {
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return Err(())
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return Err(())
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}
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unsafe {
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csr::converter_spi::data_write_write(data);
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while csr::converter_spi::pending_read() != 0 {}
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while csr::converter_spi::active_read() != 0 {}
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}
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Ok(())
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}
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}
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unsafe {
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csr::converter_spi::data_write_write(data);
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while csr::converter_spi::pending_read() != 0 {}
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while csr::converter_spi::active_read() != 0 {}
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}
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Ok(())
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}
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#[cfg(has_converter_spi)]
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pub fn read(busno: u8) -> Result<u32, ()> {
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pub fn read(busno: u8) -> Result<u32, ()> {
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if busno != 0 {
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if busno != 0 {
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return Err(())
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return Err(())
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}
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Ok(unsafe {
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csr::converter_spi::data_read_read()
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})
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}
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}
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Ok(unsafe {
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csr::converter_spi::data_read_read()
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})
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}
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}
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#[cfg(not(has_converter_spi))]
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#[cfg(not(has_converter_spi))]
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pub fn set_config(_busno: u8, _flags: u8, _write_div: u8, _read_div: u8) -> Result<(), ()> { Err(()) }
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mod imp {
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#[cfg(not(has_converter_spi))]
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pub fn set_config(_busno: u8, _flags: u8, _write_div: u8, _read_div: u8) -> Result<(), ()> { Err(()) }
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pub fn set_xfer(_busno: u8,_chip_select: u16, _write_length: u8, _read_length: u8) -> Result<(), ()> { Err(()) }
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pub fn set_xfer(_busno: u8,_chip_select: u16, _write_length: u8, _read_length: u8)
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#[cfg(not(has_converter_spi))]
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-> Result<(), ()> { Err(()) }
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pub fn write(_busno: u8,_data: u32) -> Result<(), ()> { Err(()) }
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pub fn write(_busno: u8,_data: u32) -> Result<(), ()> { Err(()) }
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#[cfg(not(has_converter_spi))]
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pub fn read(_busno: u8,) -> Result<u32, ()> { Err(()) }
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pub fn read(_busno: u8,) -> Result<u32, ()> { Err(()) }
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}
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pub use self::imp::*;
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@ -56,7 +56,7 @@ fn startup() {
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info!("gateware version {}", board::ident::read(&mut [0; 64]));
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info!("gateware version {}", board::ident::read(&mut [0; 64]));
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#[cfg(has_serwb_phy_amc)]
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#[cfg(has_serwb_phy_amc)]
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board::serwb::wait_init();
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board_artiq::serwb::wait_init();
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let t = board::clock::get_ms();
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let t = board::clock::get_ms();
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info!("press 'e' to erase startup and idle kernels...");
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info!("press 'e' to erase startup and idle kernels...");
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@ -75,9 +75,9 @@ fn startup() {
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#[cfg(si5324_free_running)]
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#[cfg(si5324_free_running)]
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setup_si5324_free_running();
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setup_si5324_free_running();
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#[cfg(has_hmc830_7043)]
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#[cfg(has_hmc830_7043)]
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board::hmc830_7043::init().expect("cannot initialize HMC830/7043");
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board_artiq::hmc830_7043::init().expect("cannot initialize HMC830/7043");
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#[cfg(has_ad9154)]
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#[cfg(has_ad9154)]
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board::ad9154::init().expect("cannot initialize AD9154");
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board_artiq::ad9154::init().expect("cannot initialize AD9154");
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#[cfg(has_ethmac)]
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#[cfg(has_ethmac)]
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startup_ethernet();
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startup_ethernet();
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