mirror of https://github.com/m-labs/artiq.git
moninj.rs: force u32 dds_ftws
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parent
6d07a16c62
commit
8eff8586bb
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@ -18,7 +18,7 @@ fn worker(socket: &mut UdpSocket) -> io::Result<()> {
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match request {
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match request {
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Request::Monitor => {
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Request::Monitor => {
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let mut dds_ftws = [0; (csr::CONFIG_RTIO_DDS_COUNT as usize *
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let mut dds_ftws = [0u32; (csr::CONFIG_RTIO_DDS_COUNT as usize *
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csr::CONFIG_DDS_CHANNELS_PER_BUS as usize)];
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csr::CONFIG_DDS_CHANNELS_PER_BUS as usize)];
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let mut reply = Reply::default();
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let mut reply = Reply::default();
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@ -54,7 +54,7 @@ fn worker(socket: &mut UdpSocket) -> io::Result<()> {
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csr::rtio_moninj::mon_probe_sel_write(i as u8);
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csr::rtio_moninj::mon_probe_sel_write(i as u8);
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csr::rtio_moninj::mon_value_update_write(1);
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csr::rtio_moninj::mon_value_update_write(1);
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dds_ftws[(csr::CONFIG_DDS_CHANNELS_PER_BUS * j + i) as usize] =
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dds_ftws[(csr::CONFIG_DDS_CHANNELS_PER_BUS * j + i) as usize] =
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csr::rtio_moninj::mon_value_read();
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csr::rtio_moninj::mon_value_read() as u32;
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}
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}
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}
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}
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}
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}
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