mirror of https://github.com/m-labs/artiq.git
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commit
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@ -163,7 +163,7 @@ class Channel(Module, SatAddMixin):
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self.u.latency += 1 # self.o
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self.u.latency += 1 # self.o
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b.p.latency += 1 # self.o
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b.p.latency += 1 # self.o
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b.f.latency += 1 # self.o
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b.f.latency += 1 # self.o
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a_latency_delta = hbf[0].latency + b.latency + 2 # hbf.i, self.o
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a_latency_delta = hbf[0].latency + b.latency + 3 # hbf.i, self.o
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for a in a1, a2:
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for a in a1, a2:
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a.a.latency += a_latency_delta
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a.a.latency += a_latency_delta
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a.p.latency += a_latency_delta
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a.p.latency += a_latency_delta
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