From 8dd9a6d02443e912b9be37c9b9c18dbc47da2739 Mon Sep 17 00:00:00 2001 From: cw-mlabs <68726632+cw-mlabs@users.noreply.github.com> Date: Mon, 27 Jul 2020 12:57:29 +0800 Subject: [PATCH] wrpll: fix scl signal --- artiq/gateware/drtio/wrpll/si549.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/artiq/gateware/drtio/wrpll/si549.py b/artiq/gateware/drtio/wrpll/si549.py index f4427a9bc..57e009a4c 100644 --- a/artiq/gateware/drtio/wrpll/si549.py +++ b/artiq/gateware/drtio/wrpll/si549.py @@ -296,8 +296,8 @@ class Si549(Module, AutoCSR): ts_scl.o.eq(self.gpio_out.storage[0]), ts_scl.oe.eq(self.gpio_oe.storage[0]) ).Else( - ts_scl.o.eq(programmer.scl), - ts_scl.oe.eq(1) + ts_scl.o.eq(0), + ts_scl.oe.eq(~programmer.scl) ) ]