mirror of https://github.com/m-labs/artiq.git
pipistrello: set RTIO_SPI_CHANNEL
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@ -200,6 +200,7 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
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spi_pins.cs_n = pmod.d[3:]
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phy = spi.SPIMaster(spi_pins)
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self.submodules += phy
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self.config["RTIO_SPI_CHANNEL"] = len(rtio_channels)
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rtio_channels.append(rtio.Channel.from_phy(
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phy, ofifo_depth=4, ififo_depth=4))
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