mirror of https://github.com/m-labs/artiq.git
test: relax test_pulse_rate on Zynq
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@ -12,6 +12,7 @@ from artiq.coredevice import exceptions
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from artiq.coredevice.comm_mgmt import CommMgmt
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from artiq.coredevice.comm_analyzer import (StoppedMessage, OutputMessage, InputMessage,
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decode_dump, get_analyzer_dump)
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from artiq.compiler.targets import CortexA9Target
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artiq_low_latency = os.getenv("ARTIQ_LOW_LATENCY")
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@ -460,10 +461,14 @@ class CoredeviceTest(ExperimentCase):
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def test_pulse_rate(self):
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"""Minimum interval for sustained TTL output switching"""
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self.execute(PulseRate)
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exp = self.execute(PulseRate)
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rate = self.dataset_mgr.get("pulse_rate")
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print(rate)
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self.assertGreater(rate, 100*ns)
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if exp.core.target_cls == CortexA9Target:
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# Crappy AXI PS/PL interface from Xilinx is slow.
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self.assertLess(rate, 810*ns)
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else:
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self.assertLess(rate, 480*ns)
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def test_pulse_rate_ad9914_dds(self):
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