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test: relax test_pulse_rate on Zynq

This commit is contained in:
Sebastien Bourdeauducq 2020-09-01 17:08:26 +08:00
parent f294d039b3
commit 8d5dc0ad2a
1 changed files with 7 additions and 2 deletions
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7
artiq/test/coredevice/test_rtio.py
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@ -12,6 +12,7 @@ from artiq.coredevice import exceptions
from artiq.coredevice.comm_mgmt import CommMgmt from artiq.coredevice.comm_mgmt import CommMgmt
from artiq.coredevice.comm_analyzer import (StoppedMessage, OutputMessage, InputMessage, from artiq.coredevice.comm_analyzer import (StoppedMessage, OutputMessage, InputMessage,
decode_dump, get_analyzer_dump) decode_dump, get_analyzer_dump)
from artiq.compiler.targets import CortexA9Target
artiq_low_latency = os.getenv("ARTIQ_LOW_LATENCY") artiq_low_latency = os.getenv("ARTIQ_LOW_LATENCY")
@ -460,10 +461,14 @@ class CoredeviceTest(ExperimentCase):
def test_pulse_rate(self): def test_pulse_rate(self):
"""Minimum interval for sustained TTL output switching""" """Minimum interval for sustained TTL output switching"""
self.execute(PulseRate) exp = self.execute(PulseRate)
rate = self.dataset_mgr.get("pulse_rate") rate = self.dataset_mgr.get("pulse_rate")
print(rate) print(rate)
self.assertGreater(rate, 100*ns) self.assertGreater(rate, 100*ns)
if exp.core.target_cls == CortexA9Target:
# Crappy AXI PS/PL interface from Xilinx is slow.
self.assertLess(rate, 810*ns)
else:
self.assertLess(rate, 480*ns) self.assertLess(rate, 480*ns)
def test_pulse_rate_ad9914_dds(self): def test_pulse_rate_ad9914_dds(self):