M-Labs
/
artiq
mirror of https://github.com/m-labs/artiq.git
2
0
Fork 2
Code Issues Projects Releases Wiki Activity

doc/manual: add FPGA board info and TTL line assignments

This commit is contained in:
Sebastien Bourdeauducq 2014-11-21 16:39:22 -08:00
parent 35d4f75b65
commit 8d59f843fb
1 changed files with 26 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

26
doc/manual/fpga_board_ports.rst Normal file
View File

@ -0,0 +1,26 @@
FPGA board ports
================
KC705
-----
The main target board for the ARTIQ core device is the KC705 development board from Xilinx.
Papilio Pro
-----------
The low-cost Papilio Pro FPGA board can be used with some limitations.
When plugged to a QC-DAQ LVDS adapter, the AD9858 DDS hardware can be used in addition to a limited number of TTL channels. The TTL lines are mapped to RTIO channels as follows:
+--------------+----------+----------------+
| RTIO channel | TTL line | Capability |
+==============+==========+================+
| 0 | PMT0 | Output + input |
+--------------+----------+----------------+
| 1 | TTL0 | Output only |
+--------------+----------+----------------+
| 2 | TTL1 | Output only |
+--------------+----------+----------------+
| 3 | TTL2 | Output only |
+--------------+----------+----------------+