diff --git a/artiq/gateware/drtio/rt_ios_satellite.py b/artiq/gateware/drtio/rt_ios_satellite.py
index 79cd0b72b..74e7cb80c 100644
--- a/artiq/gateware/drtio/rt_ios_satellite.py
+++ b/artiq/gateware/drtio/rt_ios_satellite.py
@@ -112,6 +112,8 @@ class IOS(Module):
         if fine_ts_width:
             self.sync.rio += interface.fine_ts.eq(fifo_out.timestamp[:fine_ts_width])
 
+        self.sync.rio += If(interface.stb & interface.busy, self.busy.eq(1))
+
     def add_input(self, n, channel):
         rt_packet = self.rt_packet