M-Labs
/
artiq
mirror of https://github.com/m-labs/artiq.git
2
0
Fork 2
Code Issues Projects Releases Wiki Activity

drtio: update test

This commit is contained in:
Sebastien Bourdeauducq 2016-11-24 00:37:53 +08:00
parent 7cd27abaa6
commit 8b736ddbc9
1 changed files with 10 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
artiq/test/gateware/drtio/test_full_stack.py
View File

@ -40,8 +40,9 @@ class DUT(Module):
self.ttl0 = Signal() self.ttl0 = Signal()
self.ttl1 = Signal() self.ttl1 = Signal()
self.transceivers = DummyTransceiverPair(nwords) self.transceivers = DummyTransceiverPair(nwords)
self.submodules.master = DRTIOMaster(self.transceivers.alice) self.submodules.master = DRTIOMaster(self.transceivers.alice)
self.submodules.master_ki = rtio.KernelInitiator(self.master.cri)
rx_synchronizer = DummyRXSynchronizer() rx_synchronizer = DummyRXSynchronizer()
self.submodules.phy0 = ttl_simple.Output(self.ttl0) self.submodules.phy0 = ttl_simple.Output(self.ttl0)
@ -59,7 +60,7 @@ class TestFullStack(unittest.TestCase):
def test_controller(self): def test_controller(self):
dut = DUT(2) dut = DUT(2)
kcsrs = dut.master.rt_controller.kcsrs kcsrs = dut.master_ki
csrs = dut.master.rt_controller.csrs csrs = dut.master.rt_controller.csrs
mgr = dut.master.rt_manager mgr = dut.master.rt_manager
@ -160,7 +161,7 @@ class TestFullStack(unittest.TestCase):
self.assertEqual(wlen, 2) self.assertEqual(wlen, 2)
def test_tsc_error(): def test_tsc_error():
err_present = yield from mgr.err_present.read() err_present = yield from mgr.packet_err_present.read()
self.assertEqual(err_present, 0) self.assertEqual(err_present, 0)
yield from csrs.tsc_correction.write(10000000) yield from csrs.tsc_correction.write(10000000)
yield from csrs.set_time.write(1) yield from csrs.set_time.write(1)
@ -170,17 +171,17 @@ class TestFullStack(unittest.TestCase):
yield from write(0, 1) yield from write(0, 1)
for i in range(10): for i in range(10):
yield yield
err_present = yield from mgr.err_present.read() err_present = yield from mgr.packet_err_present.read()
err_code = yield from mgr.err_code.read() err_code = yield from mgr.packet_err_code.read()
self.assertEqual(err_present, 1) self.assertEqual(err_present, 1)
self.assertEqual(err_code, 3) self.assertEqual(err_code, 3)
yield from mgr.err_present.write(1) yield from mgr.packet_err_present.write(1)
yield yield
err_present = yield from mgr.err_present.read() err_present = yield from mgr.packet_err_present.read()
self.assertEqual(err_present, 0) self.assertEqual(err_present, 0)
def test(): def test():
while not (yield dut.master.link_layer.ready): while not (yield from dut.master.link_layer.link_status.read()):
yield yield
yield from test_init() yield from test_init()
@ -214,7 +215,7 @@ class TestFullStack(unittest.TestCase):
mgr = dut.master.rt_manager mgr = dut.master.rt_manager
def test(): def test():
while not (yield dut.master.link_layer.ready): while not (yield from dut.master.link_layer.link_status.read()):
yield yield
yield from mgr.update_packet_cnt.write(1) yield from mgr.update_packet_cnt.write(1)