runtime: refactor ttl*()

* remove rt2wb_output
* remove ttl_*() ttl.c ttl.h
* use rtio_output() and rtio_input_timestamp()
* adapt coredevice/compiler layer
* adapt bridge to not artiq_raise_from_c()
This commit is contained in:
Robert Jördens 2016-03-01 16:34:05 +01:00
parent aa10791ddf
commit 8adef12781
14 changed files with 51 additions and 116 deletions

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@ -2,12 +2,6 @@ from artiq.language.core import *
from artiq.language.types import *
@syscall
def rt2wb_output(time_mu: TInt64, channel: TInt32, addr: TInt32, data: TInt32
) -> TNone:
raise NotImplementedError("syscall not simulated")
@syscall
def rt2wb_input(channel: TInt32) -> TInt32:
raise NotImplementedError("syscall not simulated")

13
artiq/coredevice/rtio.py Normal file
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@ -0,0 +1,13 @@
from artiq.language.core import syscall
from artiq.language.types import TInt64, TInt32, TNone
@syscall
def rtio_output(time_mu: TInt64, channel: TInt32, addr: TInt32, data: TInt32
) -> TNone:
raise NotImplementedError("syscall not simulated")
@syscall
def rtio_input_timestamp(timeout_mu: TInt64, channel: TInt32) -> TInt64:
raise NotImplementedError("syscall not simulated")

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@ -1,7 +1,8 @@
from artiq.language.core import (kernel, seconds_to_mu, now_mu,
delay_mu, int)
from artiq.language.units import MHz
from artiq.coredevice.rt2wb import rt2wb_output, rt2wb_input
from artiq.coredevice.rtio import rtio_output as rt2wb_output
from artiq.coredevice.rt2wb import rt2wb_input
SPI_DATA_ADDR, SPI_XFER_ADDR, SPI_CONFIG_ADDR = range(3)

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@ -1,26 +1,6 @@
from artiq.language.core import *
from artiq.language.types import *
@syscall
def ttl_set_o(time_mu: TInt64, channel: TInt32, enabled: TBool) -> TNone:
raise NotImplementedError("syscall not simulated")
@syscall
def ttl_set_oe(time_mu: TInt64, channel: TInt32, enabled: TBool) -> TNone:
raise NotImplementedError("syscall not simulated")
@syscall
def ttl_set_sensitivity(time_mu: TInt64, channel: TInt32, sensitivity: TInt32) -> TNone:
raise NotImplementedError("syscall not simulated")
@syscall
def ttl_get(channel: TInt32, time_limit_mu: TInt64) -> TInt64:
raise NotImplementedError("syscall not simulated")
@syscall
def ttl_clock_set(time_mu: TInt64, channel: TInt32, ftw: TInt32) -> TNone:
raise NotImplementedError("syscall not simulated")
from artiq.coredevice.rtio import rtio_output, rtio_input_timestamp
class TTLOut:
@ -39,7 +19,7 @@ class TTLOut:
@kernel
def set_o(self, o):
ttl_set_o(now_mu(), self.channel, o)
rtio_output(now_mu(), self.channel, 0, 1 if o else 0)
self.o_previous_timestamp = now_mu()
@kernel
@ -108,7 +88,7 @@ class TTLInOut:
@kernel
def set_oe(self, oe):
ttl_set_oe(now_mu(), self.channel, oe)
rtio_output(now_mu(), self.channel, 1, 1 if oe else 0)
@kernel
def output(self):
@ -128,7 +108,7 @@ class TTLInOut:
@kernel
def set_o(self, o):
ttl_set_o(now_mu(), self.channel, o)
rtio_output(now_mu(), self.channel, 0, 1 if o else 0)
self.o_previous_timestamp = now_mu()
@kernel
@ -170,7 +150,7 @@ class TTLInOut:
@kernel
def _set_sensitivity(self, value):
ttl_set_sensitivity(now_mu(), self.channel, value)
rtio_output(now_mu(), self.channel, 2, 1 if value else 0)
self.i_previous_timestamp = now_mu()
@kernel
@ -226,7 +206,7 @@ class TTLInOut:
"""Poll the RTIO input during all the previously programmed gate
openings, and returns the number of registered events."""
count = 0
while ttl_get(self.channel, self.i_previous_timestamp) >= 0:
while rtio_input_timestamp(self.i_previous_timestamp, self.channel) >= 0:
count += 1
return count
@ -237,7 +217,7 @@ class TTLInOut:
If the gate is permanently closed, returns a negative value.
"""
return ttl_get(self.channel, self.i_previous_timestamp)
return rtio_input_timestamp(self.i_previous_timestamp, self.channel)
class TTLClockGen:
@ -288,7 +268,7 @@ class TTLClockGen:
that are not powers of two cause jitter of one RTIO clock cycle at the
output.
"""
ttl_clock_set(now_mu(), self.channel, frequency)
rtio_output(now_mu(), self.channel, 0, frequency)
self.previous_timestamp = now_mu()
@kernel

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@ -7,7 +7,7 @@ OBJECTS := isr.o clock.o rtiocrg.o flash_storage.o mailbox.o \
session.o log.o analyzer.o moninj.o net_server.o bridge_ctl.o \
ksupport_data.o kloader.o test_mode.o main.o
OBJECTS_KSUPPORT := ksupport.o artiq_personality.o mailbox.o \
bridge.o rtio.o ttl.o rt2wb.o dds.o
bridge.o rtio.o rt2wb.o dds.o
CFLAGS += -I$(LIBALLOC_DIRECTORY) \
-I$(MISOC_DIRECTORY)/software/include/dyld \

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@ -1,21 +1,25 @@
#include "mailbox.h"
#include "messages.h"
#include "rtio.h"
#include "ttl.h"
#include "dds.h"
#include "bridge.h"
#define TIME_BUFFER (8000 << CONFIG_RTIO_FINE_TS_WIDTH)
static void dds_write(int addr, int data)
static void rtio_output_blind(int channel, int addr, int data)
{
rtio_chan_sel_write(CONFIG_RTIO_DDS_CHANNEL);
rtio_chan_sel_write(channel);
rtio_o_address_write(addr);
rtio_o_data_write(data);
rtio_o_timestamp_write(rtio_get_counter() + TIME_BUFFER);
rtio_o_we_write(1);
}
static void dds_write(int addr, int data)
{
rtio_output_blind(CONFIG_RTIO_DDS_CHANNEL, addr, data);
}
static int dds_read(int addr)
{
int r;
@ -54,7 +58,7 @@ void bridge_main(void)
struct msg_brg_ttl_out *msg;
msg = (struct msg_brg_ttl_out *)umsg;
ttl_set_oe(rtio_get_counter() + TIME_BUFFER, msg->channel, msg->value);
rtio_output_blind(msg->channel, 0, msg->value);
mailbox_acknowledge();
break;
}
@ -62,7 +66,7 @@ void bridge_main(void)
struct msg_brg_ttl_out *msg;
msg = (struct msg_brg_ttl_out *)umsg;
ttl_set_o(rtio_get_counter() + TIME_BUFFER, msg->channel, msg->value);
rtio_output_blind(msg->channel, 1, msg->value);
mailbox_acknowledge();
break;
}

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@ -2,7 +2,7 @@
#include <stdio.h>
#include "artiq_personality.h"
#include "rt2wb.h"
#include "rtio.h"
#include "log.h"
#include "dds.h"
@ -26,7 +26,7 @@
#endif
#define DDS_WRITE(addr, data) do { \
rt2wb_output(now, CONFIG_RTIO_DDS_CHANNEL, addr, data); \
rtio_output(now, CONFIG_RTIO_DDS_CHANNEL, addr, data); \
now += DURATION_WRITE; \
} while(0)

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@ -13,7 +13,6 @@
#include "messages.h"
#include "bridge.h"
#include "artiq_personality.h"
#include "ttl.h"
#include "dds.h"
#include "rtio.h"
#include "rt2wb.h"
@ -110,19 +109,14 @@ static const struct symbol runtime_exports[] = {
/* direct syscalls */
{"rtio_get_counter", &rtio_get_counter},
{"rtio_log", &rtio_log},
{"ttl_set_o", &ttl_set_o},
{"ttl_set_oe", &ttl_set_oe},
{"ttl_set_sensitivity", &ttl_set_sensitivity},
{"ttl_get", &ttl_get},
{"ttl_clock_set", &ttl_clock_set},
{"rtio_output", &rtio_output},
{"rtio_input_timestamp", &rtio_input_timestamp},
{"dds_init", &dds_init},
{"dds_batch_enter", &dds_batch_enter},
{"dds_batch_exit", &dds_batch_exit},
{"dds_set", &dds_set},
{"rt2wb_output", &rt2wb_output},
{"rt2wb_input", &rt2wb_input},
{"cache_get", &cache_get},

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@ -5,13 +5,6 @@
#include "rt2wb.h"
void rt2wb_output(long long int timestamp, int channel, int addr,
unsigned int data)
{
rtio_output(timestamp, channel, addr, data);
}
unsigned int rt2wb_input(int channel)
{
unsigned int data;

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@ -3,10 +3,7 @@
#include "rtio.h"
void rt2wb_output(long long int timestamp, int channel, int addr,
unsigned int data);
unsigned int rt2wb_input(int channel);
unsigned int rt2wb_input_sync(long long int timeout, int channel);
#endif /* __RT2WB_H */

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@ -56,8 +56,9 @@ void rtio_output(long long int timestamp, int channel, unsigned int addr,
}
int rtio_input_wait(long long int timeout, int channel)
long long int rtio_input_timestamp(long long int timeout, int channel)
{
long long int r;
int status;
rtio_chan_sel_write(channel);
@ -76,7 +77,17 @@ int rtio_input_wait(long long int timeout, int channel)
}
/* input FIFO is empty - keep waiting */
}
return status;
if (status & RTIO_I_STATUS_OVERFLOW)
artiq_raise_from_c("RTIOOverflow",
"RTIO input overflow on channel {0}",
channel, 0, 0);
if (status & RTIO_I_STATUS_EMPTY)
return -1;
r = rtio_i_timestamp_read();
rtio_i_re_write(1);
return r;
}

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@ -19,6 +19,6 @@ void rtio_log(long long int timestamp, const char *format, ...);
void rtio_log_va(long long int timestamp, const char *format, va_list args);
void rtio_output(long long int timestamp, int channel, unsigned int address,
unsigned int data);
int rtio_input_wait(long long int timeout, int channel);
long long int rtio_input_timestamp(long long int timeout, int channel);
#endif /* __RTIO_H */

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@ -1,42 +0,0 @@
#include <generated/csr.h>
#include "artiq_personality.h"
#include "rtio.h"
#include "ttl.h"
void ttl_set_o(long long int timestamp, int channel, int value)
{
rtio_output(timestamp, channel, 0, value);
}
void ttl_set_oe(long long int timestamp, int channel, int oe)
{
rtio_output(timestamp, channel, 1, oe);
}
void ttl_set_sensitivity(long long int timestamp, int channel, int sensitivity)
{
rtio_output(timestamp, channel, 2, sensitivity);
}
long long int ttl_get(int channel, long long int time_limit)
{
long long int r;
int status = rtio_input_wait(time_limit, channel);
if (status & RTIO_I_STATUS_OVERFLOW)
artiq_raise_from_c("RTIOOverflow",
"RTIO input overflow on channel {0}",
channel, 0, 0);
if (status & RTIO_I_STATUS_EMPTY)
return -1;
r = rtio_i_timestamp_read();
rtio_i_re_write(1);
return r;
}
void ttl_clock_set(long long int timestamp, int channel, int ftw)
{
rtio_output(timestamp, channel, 0, ftw);
}

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@ -1,10 +0,0 @@
#ifndef __TTL_H
#define __TTL_H
void ttl_set_o(long long int timestamp, int channel, int value);
void ttl_set_oe(long long int timestamp, int channel, int oe);
void ttl_set_sensitivity(long long int timestamp, int channel, int sensitivity);
long long int ttl_get(int channel, long long int time_limit);
void ttl_clock_set(long long int timestamp, int channel, int ftw);
#endif /* __TTL_H */