From 8aaeaa604e49a32f24a77748e5bbd7dffcd3a9da Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Robert=20J=C3=B6rdens?= Date: Mon, 7 Sep 2020 16:06:35 +0000 Subject: [PATCH] phaser: share_lut --- artiq/gateware/rtio/phy/phaser.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/artiq/gateware/rtio/phy/phaser.py b/artiq/gateware/rtio/phy/phaser.py index cc6ffa1e5..f8fe99548 100644 --- a/artiq/gateware/rtio/phy/phaser.py +++ b/artiq/gateware/rtio/phy/phaser.py @@ -6,13 +6,13 @@ from .fastlink import SerDes, SerInterface class DDSChannel(Module): - def __init__(self, use_lut=None): + def __init__(self, share_lut=None): self.rtlink = rtlink.Interface( rtlink.OInterface(data_width=32, address_width=4, enable_replace=True)) to_rio_phy = ClockDomainsRenamer("rio_phy") self.submodules.dds = to_rio_phy(MultiDDS( - n=5, fwidth=32, xwidth=16, z=19, zl=10, use_lut=use_lut)) + n=5, fwidth=32, xwidth=16, z=19, zl=10, shae_lut=share_lut)) regs = [] for i in self.dds.i: regs.extend([i.f, Cat(i.a, i.clr, i.p)]) @@ -32,7 +32,7 @@ class Phaser(Module): # share a CosSinGen LUT between the two channels self.submodules.ch0 = DDSChannel() - self.submodules.ch1 = DDSChannel(use_lut=self.ch0.dds.mod.cs.lut) + self.submodules.ch1 = DDSChannel(share_lut=self.ch0.dds.mod.cs.lut) n_channels = 2 n_samples = 8 n_bits = 14