coredevice: use NAC3 exception support

artiq/coredevice/ad53xx.py

@@ -110,8 +110,7 @@ def voltage_to_mu(voltage: float, offset_dacs: int32 = 0x2000, vref: float = 5.)
     """
     code = round(float(1 << 16) * (voltage / (4. * vref))) + offset_dacs * 0x4
     if code < 0x0 or code > 0xffff:
-        # NAC3TODO raise ValueError("Invalid DAC voltage!")
+        raise ValueError("Invalid DAC voltage!")
-        pass
     return code
 
 
@@ -197,19 +196,16 @@ class AD53xx:
         if not blind:
             ctrl = self.read_reg(0, AD53XX_READ_CONTROL)
             if ctrl == 0xffff:
-                # NAC3TODO raise ValueError("DAC not found")
+                raise ValueError("DAC not found")
-                pass
             if (ctrl & 0b10000) != 0:
-                # NAC3TODO raise ValueError("DAC over temperature")
+                raise ValueError("DAC over temperature")
-                pass
             self.core.delay(25.*us)
         self.bus.write(  # enable power and overtemperature shutdown
             (AD53XX_CMD_SPECIAL | AD53XX_SPECIAL_CONTROL | 0b0010) << 8)
         if not blind:
             ctrl = self.read_reg(0, AD53XX_READ_CONTROL)
             if (ctrl & 0b10111) != 0b00010:
-                # NAC3TODO raise ValueError("DAC CONTROL readback mismatch")
+                raise ValueError("DAC CONTROL readback mismatch")
-                pass
             self.core.delay(15.*us)
 
     @kernel

artiq/coredevice/ad9912.py

@@ -112,8 +112,7 @@ class AD9912:
         # Verify chip ID and presence
         prodid = self.read(AD9912_PRODIDH, 2)
         if (prodid != 0x1982) and (prodid != 0x1902):
-            # NAC3TODO raise ValueError("Urukul AD9912 product id mismatch")
+            raise ValueError() # NAC3TODO("Urukul AD9912 product id mismatch")
-            pass
         self.core.delay(50. * us)
         # HSTL power down, CMOS power down
         self.write(AD9912_PWRCNTRL1, 0x80, 1)

artiq/coredevice/adf5356.py

@@ -103,8 +103,7 @@ class ADF5356:
             self.sync()
             self.core.delay(1000. * us)
             if not self.read_muxout():
-                # NAC3TODO raise ValueError("MUXOUT not high")
+                raise ValueError("MUXOUT not high")
-                pass
             self.core.delay(800. * us)
 
             # MUXOUT = DGND
@@ -112,8 +111,7 @@ class ADF5356:
             self.sync()
             self.core.delay(1000. * us)
             if self.read_muxout():
-                # NAC3TODO raise ValueError("MUXOUT not low")
+                raise ValueError("MUXOUT not low")
-                pass
             self.core.delay(800. * us)
 
             # MUXOUT = digital lock-detect
@@ -152,8 +150,7 @@ class ADF5356:
         :param n: output power setting, 0, 1, 2, or 3 (see ADF5356 datasheet, fig. 44).
         """
         if not 0 <= n <= 3:
-            # NAC3TODO raise ValueError("invalid power setting")
+            raise ValueError("invalid power setting")
-            pass
         self.regs[6] = ADF5356_REG6_RF_OUTPUT_A_POWER_UPDATE(self.regs[6], n)
         self.sync()
 
@@ -190,8 +187,7 @@ class ADF5356:
         freq = round64(f)
 
         if freq > ADF5356_MAX_VCO_FREQ:
-            # NAC3TODO raise ValueError("Requested too high frequency")
+            raise ValueError("Requested too high frequency")
-            pass
 
         # select minimal output divider
         rf_div_sel = 0
@@ -200,8 +196,7 @@ class ADF5356:
             rf_div_sel += 1
 
         if (1 << rf_div_sel) > 64:
-            # NAC3TODO raise ValueError("Requested too low frequency")
+            raise ValueError("Requested too low frequency")
-            pass
 
         # choose reference divider that maximizes PFD frequency
         self.regs[4] = ADF5356_REG4_R_COUNTER_UPDATE(
@@ -229,8 +224,7 @@ class ADF5356:
         )
 
         if not (n_min <= n <= n_max):
-            # NAC3TODO raise ValueError("Invalid INT value")
+            raise ValueError("Invalid INT value")
-            pass
 
         # configure PLL
         self.regs[0] = ADF5356_REG0_INT_VALUE_UPDATE(self.regs[0], n)

artiq/coredevice/mirny.py

@@ -132,16 +132,14 @@ class Mirny:
 
         if not blind:
             if (reg0 >> 2) & 0x3 != PROTO_REV_MATCH:
-                # NAC3TODO raise ValueError("Mirny PROTO_REV mismatch")
+                raise ValueError("Mirny PROTO_REV mismatch")
-                pass
             self.core.delay(100. * us)  # slack
 
         # select clock source
         self.clk_sel = self.clk_sel_hw_rev[self.hw_rev]
 
         if self.clk_sel < 0:
-            # NAC3TODO raise ValueError("Hardware revision not supported")
+            raise ValueError("Hardware revision not supported")
-            pass
 
         self.write_reg(1, (self.clk_sel << 4))
         self.core.delay(1000. * us)

artiq/coredevice/spi2.py

@@ -174,11 +174,10 @@ class SPIMaster:
             Or number of the chip select to assert if ``cs`` is decoded
             downstream. (reset=0)
         """
-        # NAC3TODO
+        if length > 32 or length < 1:
-        #if length > 32 or length < 1:
+            raise ValueError("Invalid SPI transfer length")
-        #    raise ValueError("Invalid SPI transfer length")
+        if div > 257 or div < 2:
-        #if div > 257 or div < 2:
+            raise ValueError("Invalid SPI clock divider")
-        #    raise ValueError("Invalid SPI clock divider")
         rtio_output((self.channel << 8) | SPI_CONFIG_ADDR, flags |
                 ((length - 1) << 8) | ((div - 2) << 16) | (cs << 24))
         self.update_xfer_duration_mu(div, length)

artiq/coredevice/ttl.py

@@ -434,7 +434,7 @@ class TTLInOut:
         rtio_output(self.target_sample, 1)  # gate rising
         return rtio_input_data(self.channel) == 0
 
-    # NAC3TODO @kernel
+    @kernel
     def watch_done(self) -> bool:
         """Stop watching the input at the position of the time cursor.
 

artiq/coredevice/urukul.py

@@ -260,8 +260,7 @@ class CPLD:
         else:
             proto_rev = urukul_sta_proto_rev(self.sta_read())
             if proto_rev != STA_PROTO_REV_MATCH:
-                # NAC3TODO raise ValueError("Urukul proto_rev mismatch")
+                raise ValueError("Urukul proto_rev mismatch")
-                pass
         self.core.delay(100. * us)  # reset, slack
         self.cfg_write(cfg)
         if self.sync_div != 0:
@@ -317,8 +316,7 @@ class CPLD:
         """
         code = 255 - round(att * 8.)
         if code < 0 or code > 255:
-            # NAC3TODO raise ValueError("Invalid urukul.CPLD attenuation!")
+            raise ValueError("Invalid urukul.CPLD attenuation!")
-            pass
         return code
 
     @kernel