From 893be82ad167efd6a0a5924af1506d674ea1e2d6 Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Mon, 9 Oct 2017 10:22:58 +0800
Subject: [PATCH] rtio/dma: raise underflow in test

---
 artiq/gateware/test/rtio/test_dma.py | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/artiq/gateware/test/rtio/test_dma.py b/artiq/gateware/test/rtio/test_dma.py
index 8f84b37d9..d0e74b5ea 100644
--- a/artiq/gateware/test/rtio/test_dma.py
+++ b/artiq/gateware/test/rtio/test_dma.py
@@ -5,6 +5,7 @@ import itertools
 from migen import *
 from misoc.interconnect import wishbone
 
+from artiq.coredevice.exceptions import RTIOUnderflow
 from artiq.gateware import rtio
 from artiq.gateware.rtio import dma, cri
 from artiq.gateware.rtio.phy import ttl_simple
@@ -56,6 +57,8 @@ def do_dma(dut, address):
     yield
     while ((yield from dut.enable.read())):
         yield
+    if (yield from dut.cri_master.underflow.read()):
+        raise RTIOUnderflow
 
 
 test_writes1 = [