diff --git a/soc/targets/artiq_kc705.py b/soc/targets/artiq_kc705.py
index 4d9f4e830..c6cb4c071 100644
--- a/soc/targets/artiq_kc705.py
+++ b/soc/targets/artiq_kc705.py
@@ -3,7 +3,7 @@ from migen.bank.description import *
 from migen.bank import wbgen
 from mibuild.generic_platform import *
 
-from misoclib.cpu.peripherals import gpio
+from misoclib.com import gpio
 from misoclib.soc import mem_decoder
 from targets.kc705 import BaseSoC
 
diff --git a/soc/targets/artiq_pipistrello.py b/soc/targets/artiq_pipistrello.py
index 5333389d9..c5c967239 100644
--- a/soc/targets/artiq_pipistrello.py
+++ b/soc/targets/artiq_pipistrello.py
@@ -3,7 +3,7 @@ from migen.bank.description import *
 from migen.bank import wbgen
 from mibuild.generic_platform import *
 
-from misoclib.cpu.peripherals import gpio
+from misoclib.com import gpio
 from targets.pipistrello import BaseSoC
 
 from artiq.gateware import rtio, ad9858
diff --git a/soc/targets/artiq_ppro.py b/soc/targets/artiq_ppro.py
index de7f28b5f..a69cdf7fa 100644
--- a/soc/targets/artiq_ppro.py
+++ b/soc/targets/artiq_ppro.py
@@ -3,7 +3,7 @@ from migen.bank.description import *
 from migen.bank import wbgen
 from mibuild.generic_platform import *
 
-from misoclib.cpu.peripherals import gpio
+from misoclib.com import gpio
 from misoclib.mem.sdram.core.minicon import MiniconSettings
 from targets.ppro import BaseSoC