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https://github.com/m-labs/artiq.git
synced 2024-12-21 01:16:28 +08:00
drtio: implement basic writes, errors, fifo levels on satellite
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23b3302200
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87ec333f55
@ -48,8 +48,12 @@ def get_s2m_layouts(alignment):
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error_codes = {
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"frame_missed": 0,
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"unknown_type": 1
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"unknown_type": 0,
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# The transmitter is normally responsible for avoiding
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# overflows and underflows. Those error reports are only
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# for diagnosing internal ARTIQ bugs.
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"write_overflow": 1,
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"write_underflow": 2
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}
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@ -182,6 +186,21 @@ class RTPacketSatellite(Module):
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self.tsc_load = Signal()
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self.tsc_value = Signal(64)
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self.fifo_level_channel = Signal(16)
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self.fifo_level_update = Signal()
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self.fifo_level = Signal(24)
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self.write_stb = Signal()
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self.write_timestamp = Signal(64)
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self.write_channel = Signal(16)
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self.write_address = Signal(16)
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self.write_data = Signal(256)
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self.write_overflow = Signal()
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self.write_overflow_ack = Signal()
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self.write_underflow = Signal()
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self.write_underflow_ack = Signal()
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# # #
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# RX/TX datapath
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@ -200,55 +219,108 @@ class RTPacketSatellite(Module):
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self.tx_rt_data.eq(tx_dp.data)
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]
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# glue
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self.comb += [
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self.tsc_value.eq(rx_dp.packet_as["set_time"].timestamp)
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]
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# main control FSM
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fsm = FSM(reset_state="WAIT_INPUT")
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self.submodules += fsm
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continuation = Signal()
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continuation_r = Signal()
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frame_r_r = Signal()
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# RX->TX
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echo_req = Signal()
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err_set = Signal()
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err_req = Signal()
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err_ack = Signal()
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fifo_level_set = Signal()
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fifo_level_req = Signal()
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fifo_level_ack = Signal()
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self.sync += [
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continuation_r.eq(continuation),
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frame_r_r.eq(rx_dp.frame_r)
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If(err_ack, err_req.eq(0)),
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If(err_set, err_req.eq(1)),
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If(fifo_level_ack, fifo_level_req.eq(0)),
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If(fifo_level_set, fifo_level_req.eq(1)),
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]
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fsm.act("WAIT_INPUT",
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err_code = Signal(max=len(error_codes)+1)
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# RX FSM
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self.comb += [
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self.tsc_value.eq(
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rx_dp.packet_as["set_time"].timestamp),
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self.fifo_level_channel.eq(
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rx_dp.packet_as["fifo_level_request"].channel),
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self.write_timestamp.eq(
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rx_dp.packet_as["write"].timestamp),
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self.write_channel.eq(
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rx_dp.packet_as["write"].channel),
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self.write_address.eq(
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rx_dp.packet_as["write"].address),
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self.write_data.eq(
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rx_dp.packet_as["write"].short_data)
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]
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rx_fsm = FSM(reset_state="INPUT")
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self.submodules += rx_fsm
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rx_fsm.act("INPUT",
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If(rx_dp.frame_r,
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If(~frame_r_r | continuation_r,
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continuation.eq(1),
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rx_dp.packet_buffer_load.eq(1),
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If(rx_dp.packet_last,
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Case(rx_dp.packet_type, {
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rx_plm.types["echo_request"]: NextState("ECHO"),
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rx_plm.types["echo_request"]: echo_req.eq(1),
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rx_plm.types["set_time"]: NextState("SET_TIME"),
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"default": NextState("ERROR_UNKNOWN_TYPE")
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rx_plm.types["write"]: NextState("WRITE"),
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rx_plm.types["fifo_level_request"]: NextState("FIFO_LEVEL"),
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"default": [
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err_set.eq(1),
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NextValue(err_code, error_codes["unknown_type"])]
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})
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)
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).Else(
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NextState("ERROR_FRAME_MISSED")
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)
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)
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rx_fsm.act("SET_TIME",
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self.tsc_load.eq(1),
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NextState("INPUT")
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)
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fsm.act("ECHO",
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rx_fsm.act("WRITE",
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self.write_stb.eq(1),
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NextState("INPUT")
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)
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rx_fsm.act("FIFO_LEVEL",
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fifo_level_set.eq(1),
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self.fifo_level_update.eq(1),
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NextState("INPUT")
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)
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# TX FSM
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tx_fsm = FSM(reset_state="IDLE")
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self.submodules += tx_fsm
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tx_fsm.act("IDLE",
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If(echo_req, NextState("ECHO")),
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If(fifo_level_req, NextState("FIFO_LEVEL")),
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If(self.write_overflow, NextState("ERROR_WRITE_OVERFLOW")),
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If(self.write_underflow, NextState("ERROR_WRITE_UNDERFLOW")),
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If(err_req, NextState("ERROR"))
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)
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tx_fsm.act("ECHO",
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tx_dp.send("echo_reply"),
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tx_dp.stb.eq(1),
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If(tx_dp.done, NextState("WAIT_INPUT"))
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If(tx_dp.done, NextState("IDLE"))
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)
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fsm.act("SET_TIME",
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self.tsc_load.eq(1),
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NextState("WAIT_INPUT")
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)
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fsm.act("ERROR_FRAME_MISSED",
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tx_dp.send("error", code=error_codes["frame_missed"]),
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tx_fsm.act("FIFO_LEVEL",
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fifo_level_ack.eq(1),
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tx_dp.send("fifo_level_reply", level=self.fifo_level),
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tx_dp.stb.eq(1),
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If(tx_dp.done, NextState("WAIT_INPUT"))
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If(tx_dp.done, NextState("IDLE"))
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)
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fsm.act("ERROR_UNKNOWN_TYPE",
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tx_dp.send("error", code=error_codes["unknown_type"]),
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tx_fsm.act("ERROR_WRITE_OVERFLOW",
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self.write_overflow_ack.eq(1),
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tx_dp.send("error", code=error_codes["write_overflow"]),
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tx_dp.stb.eq(1),
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If(tx_dp.done, NextState("WAIT_INPUT"))
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If(tx_dp.done, NextState("IDLE"))
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)
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tx_fsm.act("ERROR_WRITE_UNDERFLOW",
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self.write_underflow_ack.eq(1),
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tx_dp.send("error", code=error_codes["write_underflow"]),
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tx_dp.stb.eq(1),
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If(tx_dp.done, NextState("IDLE"))
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)
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tx_fsm.act("ERROR",
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err_ack.eq(1),
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tx_dp.send("error", code=err_code),
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tx_dp.stb.eq(1),
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If(tx_dp.done, NextState("IDLE"))
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)
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