mirror of https://github.com/m-labs/artiq.git
artiq_ddb_template: add edge counter support
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@ -83,6 +83,7 @@ class PeripheralManager:
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class_names[peripheral["bank_direction_low"]],
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class_names[peripheral["bank_direction_high"]]
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]
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channel = count(0)
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for i in range(8):
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self.gen("""
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device_db["{name}"] = {{
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@ -94,8 +95,22 @@ class PeripheralManager:
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""",
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name=self.get_name("ttl"),
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class_name=classes[i//4],
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channel=rtio_offset+i)
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return 8
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channel=rtio_offset+next(channel))
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if peripheral.get("edge_counter", False):
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for i in range(8):
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class_name = classes[i//4]
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if class_name == "TTLInOut":
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self.gen("""
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device_db["{name}"] = {{
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"type": "local",
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"module": "artiq.coredevice.edge_counter",
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"class": "EdgeCounter",
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"arguments": {{"channel": 0x{channel:06x}}},
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}}
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""",
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name=self.get_name("ttl_counter"),
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channel=rtio_offset+next(channel))
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return next(channel)
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# TODO: support 1-EEM mode
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def process_urukul(self, rtio_offset, peripheral):
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