targets: rename AMP->Top, merge peripherals

artiq/frontend/artiq_flash.sh

@@ -90,7 +90,7 @@ fi
 if [ "$BOARD" == "kc705" ]
 then
 	UDEV_RULES=99-kc705.rules
-	BITSTREAM=artiq_kc705-artiqsocbasic-kc705.bit
+	BITSTREAM=artiq_kc705-top-kc705.bit
 	CABLE=jtaghs1_fast
 	PROXY=bscan_spi_kc705.bit
 	BIOS_ADDR=0xaf0000
@@ -100,7 +100,7 @@ then
 elif [ "$BOARD" == "pipistrello" ]
 then
 	UDEV_RULES=99-papilio.rules
-	BITSTREAM=artiq_pipistrello-amp-pipistrello.bin
+	BITSTREAM=artiq_pipistrello-top-pipistrello.bin
 	CABLE=papilio
 	PROXY=bscan_spi_lx9_csg324.bit
 	BIOS_ADDR=0x170000

soc/runtime/main.c

@@ -366,16 +366,14 @@ int main(void)
     irq_setie(1);
     uart_init();
 
-#ifdef ARTIQ_AMP
+    puts("ARTIQ runtime built "__DATE__" "__TIME__"\n");
-    puts("ARTIQ runtime built "__DATE__" "__TIME__" for AMP systems\n");
+
-#else
-    puts("ARTIQ runtime built "__DATE__" "__TIME__" for UP systems\n");
-#endif
 #ifdef CSR_ETHMAC_BASE
     puts("Accepting sessions on Ethernet");
 #else
     puts("Accepting sessions on serial link");
 #endif
+
     puts("Press 't' to enter test mode...");
     blink_led();
 

soc/targets/artiq_kc705.py

@@ -30,15 +30,17 @@ class _RTIOCRG(Module, AutoCSR):
                                   o_O=self.cd_rtio.clk)
 
 
-class _Peripherals(MiniSoC):
+class Top(MiniSoC):
     csr_map = {
         "rtio": None,  # mapped on Wishbone instead
-        "rtiocrg": 13
+        "rtiocrg": 13,
+        "kernel_cpu": 14
     }
     csr_map.update(MiniSoC.csr_map)
     mem_map = {
         "rtio":     0x20000000, # (shadow @0xa0000000)
         "dds":      0x50000000, # (shadow @0xd0000000)
+        "mailbox":  0x70000000  # (shadow @0xf0000000)
     }
     mem_map.update(MiniSoC.mem_map)
 
@@ -94,34 +96,27 @@ set_false_path -from [get_clocks rsys_clk] -to [get_clocks rio_clk]
 set_false_path -from [get_clocks rio_clk] -to [get_clocks rsys_clk]
 """, rsys_clk=self.rtio.cd_rsys.clk, rio_clk=self.rtio.cd_rio.clk)
 
-
+        # Kernel CPU
-class AMP(_Peripherals):
-    csr_map = {
-        "kernel_cpu": 14
-    }
-    csr_map.update(_Peripherals.csr_map)
-    mem_map = {
-        "mailbox":  0x70000000 # (shadow @0xf0000000)
-    }
-    mem_map.update(_Peripherals.mem_map)
-
-    def __init__(self, platform, *args, **kwargs):
-        _Peripherals.__init__(self, platform, *args, **kwargs)
-
         self.submodules.kernel_cpu = amp.KernelCPU(
             platform, self.sdram.crossbar.get_master())
         self.submodules.mailbox = amp.Mailbox()
-        self.add_wb_slave(mem_decoder(self.mem_map["mailbox"]), self.mailbox.i1)
+        self.add_wb_slave(mem_decoder(self.mem_map["mailbox"]),
-        self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["mailbox"]), self.mailbox.i2)
+                          self.mailbox.i1)
-        self.add_memory_region("mailbox", self.mem_map["mailbox"] + 0x80000000, 4)
+        self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["mailbox"]),
+                                     self.mailbox.i2)
+        self.add_memory_region("mailbox",
+                               self.mem_map["mailbox"] + 0x80000000, 4)
 
         rtio_csrs = self.rtio.get_csrs()
         self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
-        self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["rtio"]), self.rtiowb.bus)
+        self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["rtio"]),
-        self.add_csr_region("rtio", self.mem_map["rtio"] + 0x80000000, 32, rtio_csrs)
+                                     self.rtiowb.bus)
+        self.add_csr_region("rtio", self.mem_map["rtio"] + 0x80000000, 32,
+                            rtio_csrs)
 
-        self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["dds"]), self.dds.bus)
+        self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["dds"]),
+                                     self.dds.bus)
         self.add_memory_region("dds", self.mem_map["dds"] + 0x80000000, 64*4)
 
 
-default_subtarget = AMP
+default_subtarget = Top

soc/targets/artiq_pipistrello.py

@@ -51,15 +51,17 @@ TIMESPEC "TSfix_ise6" = FROM "GRPint_clk" TO "GRPext_clk" TIG;
 """, int_clk=rtio_internal_clk, ext_clk=rtio_external_clk)
 
 
-class _Peripherals(BaseSoC):
+class Top(BaseSoC):
     csr_map = {
         "rtio": None,  # mapped on Wishbone instead
-        "rtiocrg": 13
+        "rtiocrg": 13,
+        "kernel_cpu": 14
     }
     csr_map.update(BaseSoC.csr_map)
     mem_map = {
         "rtio":     0x20000000,  # (shadow @0xa0000000)
         "dds":      0x50000000,  # (shadow @0xd0000000)
+        "mailbox":  0x70000000   # (shadow @0xf0000000)
     }
     mem_map.update(BaseSoC.mem_map)
 
@@ -120,20 +122,7 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
         self.submodules.dds = ad9858.AD9858(dds_pads)
         self.comb += dds_pads.fud_n.eq(~fud)
 
-
+        # Kernel CPU
-class AMP(_Peripherals):
-    csr_map = {
-        "kernel_cpu": 14
-    }
-    csr_map.update(_Peripherals.csr_map)
-    mem_map = {
-        "mailbox":  0x70000000  # (shadow @0xf0000000)
-    }
-    mem_map.update(_Peripherals.mem_map)
-
-    def __init__(self, platform, *args, **kwargs):
-        _Peripherals.__init__(self, platform, **kwargs)
-
         self.submodules.kernel_cpu = amp.KernelCPU(
             platform, self.sdram.crossbar.get_master())
         self.submodules.mailbox = amp.Mailbox()
@@ -156,4 +145,4 @@ class AMP(_Peripherals):
         self.add_memory_region("dds", self.mem_map["dds"] + 0x80000000, 64*4)
 
 
-default_subtarget = AMP
+default_subtarget = Top