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phaser: tweaks

This commit is contained in:
Robert Jördens 2020-09-22 15:27:38 +00:00
parent 5c76f5c319
commit 85d16e3e5f
3 changed files with 12 additions and 11 deletions
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2
artiq/coredevice/dac34h84.py
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@ -32,7 +32,7 @@ class DAC34H84:
revbus = 0 revbus = 0
twos = 1 twos = 1
coarse_dac = 0xa # 20.6 mA, 0-15 coarse_dac = 9 # 18.75 mA, 0-15
sif_txenable = 0 sif_txenable = 0
mask_alarm_from_zerochk = 0 mask_alarm_from_zerochk = 0

17
artiq/coredevice/phaser.py
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@ -119,6 +119,7 @@ class Phaser:
:param core_device: Core device name (default: "core") :param core_device: Core device name (default: "core")
:param miso_delay: Fastlink MISO signal delay to account for cable :param miso_delay: Fastlink MISO signal delay to account for cable
and buffer round trip. Tuning this might be automated later. and buffer round trip. Tuning this might be automated later.
:param clk_sel: Select the external SMA clock input (1 or 0)
:param dac: DAC34H84 DAC settings as a dictionary. :param dac: DAC34H84 DAC settings as a dictionary.
:param trf0: Channel 0 TRF372017 quadrature upconverter settings as a :param trf0: Channel 0 TRF372017 quadrature upconverter settings as a
dictionary. dictionary.
@ -134,8 +135,8 @@ class Phaser:
kernel_invariants = {"core", "channel_base", "t_frame", "miso_delay", kernel_invariants = {"core", "channel_base", "t_frame", "miso_delay",
"dac_mmap"} "dac_mmap"}
def __init__(self, dmgr, channel_base, miso_delay=1, core_device="core", def __init__(self, dmgr, channel_base, miso_delay=1, clk_sel=0,
dac=None, trf0=None, trf1=None): dac=None, trf0=None, trf1=None, core_device="core"):
self.channel_base = channel_base self.channel_base = channel_base
self.core = dmgr.get(core_device) self.core = dmgr.get(core_device)
# TODO: auto-align miso-delay in phy # TODO: auto-align miso-delay in phy
@ -144,6 +145,7 @@ class Phaser:
# self.core.seconds_to_mu(10*8*4*ns) # unfortunately this returns 319 # self.core.seconds_to_mu(10*8*4*ns) # unfortunately this returns 319
assert self.core.ref_period == 1*ns assert self.core.ref_period == 1*ns
self.t_frame = 10*8*4 self.t_frame = 10*8*4
self.clk_sel = clk_sel
self.dac_mmap = DAC34H84(dac).get_mmap() self.dac_mmap = DAC34H84(dac).get_mmap()
@ -151,14 +153,13 @@ class Phaser:
for ch, trf in enumerate([trf0, trf1])] for ch, trf in enumerate([trf0, trf1])]
@kernel @kernel
def init(self, clk_sel=0): def init(self):
"""Initialize the board. """Initialize the board.
Verifies board and chip presence, resets components, performs Verifies board and chip presence, resets components, performs
communication and configuration tests and establishes initial communication and configuration tests and establishes initial
conditions. conditions.
:param clk_sel: Select the external SMA clock input (1 or 0)
""" """
board_id = self.read8(PHASER_ADDR_BOARD_ID) board_id = self.read8(PHASER_ADDR_BOARD_ID)
if board_id != PHASER_BOARD_ID: if board_id != PHASER_BOARD_ID:
@ -167,7 +168,7 @@ class Phaser:
hw_rev = self.read8(PHASER_ADDR_HW_REV) hw_rev = self.read8(PHASER_ADDR_HW_REV)
delay(.1*ms) # slack delay(.1*ms) # slack
has_upconverter = hw_rev & PHASER_HW_REV_VARIANT is_baseband = hw_rev & PHASER_HW_REV_VARIANT
gw_rev = self.read8(PHASER_ADDR_GW_REV) gw_rev = self.read8(PHASER_ADDR_GW_REV)
delay(.1*ms) # slack delay(.1*ms) # slack
@ -183,7 +184,7 @@ class Phaser:
self.set_leds(0x00) self.set_leds(0x00)
self.set_fan_mu(0) self.set_fan_mu(0)
# bring everything out of reset, keep tx off # bring everything out of reset, keep tx off
self.set_cfg(clk_sel=clk_sel, dac_txena=0) self.set_cfg(clk_sel=self.clk_sel, dac_txena=0)
# TODO: crossing dac_clk (125 MHz) edges with sync_dly (0-7 ns) # TODO: crossing dac_clk (125 MHz) edges with sync_dly (0-7 ns)
# should change the optimal fifo_offset by 4 # should change the optimal fifo_offset by 4
@ -269,7 +270,7 @@ class Phaser:
abs(data_i - data_q) > 2): abs(data_i - data_q) > 2):
raise ValueError("DUC+oscillator phase/amplitude test failed") raise ValueError("DUC+oscillator phase/amplitude test failed")
if has_upconverter: if not is_baseband:
for data in channel.trf_mmap: for data in channel.trf_mmap:
channel.trf_write(data) channel.trf_write(data)
delay(.1*ms) delay(.1*ms)
@ -279,7 +280,7 @@ class Phaser:
if not lock_detect: if not lock_detect:
raise ValueError("TRF quadrature upconverter lock failure") raise ValueError("TRF quadrature upconverter lock failure")
self.set_cfg(clk_sel=clk_sel) # txena self.set_cfg(clk_sel=self.clk_sel) # txena
@kernel @kernel
def write8(self, addr, data): def write8(self, addr, data):

4
artiq/coredevice/trf372017.py
View File

@ -12,7 +12,7 @@ class TRF372017:
cal_clk_sel = 12 # /16, 4b cal_clk_sel = 12 # /16, 4b
ndiv = 420 # 16b ndiv = 420 # 16b
pll_div_sel = 0b01 # /1, 2b pll_div_sel = 0 # /1, 2b
prsc_sel = 1 # 8/9 prsc_sel = 1 # 8/9
vco_sel = 2 # 2b vco_sel = 2 # 2b
vcosel_mode = 0 vcosel_mode = 0
@ -106,7 +106,7 @@ class TRF372017:
(self.en_extvco << 17) | (self.en_isource << 18) | (self.en_extvco << 17) | (self.en_isource << 18) |
(self.ld_ana_prec << 19) | (self.cp_tristate << 21) | (self.ld_ana_prec << 19) | (self.cp_tristate << 21) |
(self.speedup << 23) | (self.ld_dig_prec << 24) | (self.speedup << 23) | (self.ld_dig_prec << 24) |
(self.en_dith << 25) | (self.mod_ord << 27) | (self.en_dith << 25) | (self.mod_ord << 26) |
(self.dith_sel << 28) | (self.del_sd_clk << 29) | (self.dith_sel << 28) | (self.del_sd_clk << 29) |
(self.en_frac << 31)) (self.en_frac << 31))
mmap.append( mmap.append(