From 84e1f05559bdf4d95408aea051509b4646a6b8c9 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 1 May 2018 16:11:26 +0200 Subject: [PATCH] sayma_rtm: make cd_sys4x clock domain reset_less --- artiq/gateware/targets/sayma_rtm.py | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/artiq/gateware/targets/sayma_rtm.py b/artiq/gateware/targets/sayma_rtm.py index 9bb6bef55..8cffd12ad 100755 --- a/artiq/gateware/targets/sayma_rtm.py +++ b/artiq/gateware/targets/sayma_rtm.py @@ -22,7 +22,7 @@ from artiq import __version__ as artiq_version class CRG(Module): def __init__(self, platform): self.clock_domains.cd_sys = ClockDomain() - self.clock_domains.cd_sys4x = ClockDomain() + self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) self.clock_domains.cd_clk200 = ClockDomain() self.serwb_refclk = Signal() @@ -55,7 +55,6 @@ class CRG(Module): Instance("BUFG", i_I=pll_sys4x, o_O=self.cd_sys4x.clk), Instance("BUFG", i_I=pll_clk200, o_O=self.cd_clk200.clk), AsyncResetSynchronizer(self.cd_sys, ~pll_locked | self.serwb_reset), - AsyncResetSynchronizer(self.cd_sys4x, ~pll_locked | self.serwb_reset), AsyncResetSynchronizer(self.cd_clk200, ~pll_locked | self.serwb_reset) ]