From 8446cccb4eb0ff139ae1fc9366e9d13b96e8dd1a Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Thu, 13 Apr 2017 13:38:13 +0200 Subject: [PATCH] pdq2: mem_read --- artiq/coredevice/pdq2.py | 25 +++++++++++++++++++++---- 1 file changed, 21 insertions(+), 4 deletions(-) diff --git a/artiq/coredevice/pdq2.py b/artiq/coredevice/pdq2.py index 5410e7d2f..18ff1c773 100644 --- a/artiq/coredevice/pdq2.py +++ b/artiq/coredevice/pdq2.py @@ -35,7 +35,7 @@ class PDQ2: self.chip_select = chip_select @kernel - def setup_bus(self, write_div=4, read_div=15): + def setup_bus(self, write_div=24, read_div=64): """Configure the SPI bus and the SPI transaction parameters for this device. This method has to be called before any other method if the bus has been used to access a different device in the meantime. @@ -64,7 +64,7 @@ class PDQ2: delay_mu(self.bus.ref_period_mu) # get to 20ns min cs high self.bus.read_async() self.bus.set_xfer(self.chip_select, 16, 0) - return self.bus.input_async() & 0xff + return int(self.bus.input_async() & 0xff) # FIXME: m-labs/artiq#713 @kernel def write_config(self, reset=0, clk2x=0, enable=1, @@ -94,7 +94,7 @@ class PDQ2: return self.read_reg(_PDQ2_ADR_FRAME, board) @kernel - def write_mem(self, mem, adr, data, board=0xf): + def write_mem(self, mem, adr, data, board=0xf): # FIXME: m-labs/artiq#714 self.bus.set_xfer(self.chip_select, 24, 0) self.bus.write((_PDQ2_CMD(board, 1, mem, 1) << 24) | ((adr & 0x00ff) << 16) | (adr & 0xff00)) @@ -108,4 +108,21 @@ class PDQ2: @kernel def read_mem(self, mem, adr, data, board=0xf): - pass + self.bus.set_xfer(self.chip_select, 24, 8) + self.bus.write((_PDQ2_CMD(board, 1, mem, 0) << 24) | + ((adr & 0x00ff) << 16) | (adr & 0xff00)) + delay_mu(-self.bus.write_period_mu-3*self.bus.ref_period_mu) + self.bus.set_xfer(self.chip_select, 0, 16) + for i in range(len(data)//2): + self.bus.write(0) + delay_mu(-self.bus.write_period_mu-3*self.bus.ref_period_mu) + self.bus.read_async() + d = self.bus.input_async() + data[2*i] = (d >> 8) & 0xff + data[2*i + 1] = d & 0xff + return int(self.bus.input_async() & 0xff) # FIXME: m-labs/artiq#713 + delay_mu(self.bus.write_period_mu + self.bus.ref_period_mu) + # get to 20ns min cs high + self.bus.set_xfer(self.chip_select, 16, 0) + + pass