M-Labs
/
artiq
mirror of https://github.com/m-labs/artiq.git
2
0
Fork 2
Code Issues Projects Releases Wiki Activity

rtio: break DMA timing path

This commit is contained in:
Sebastien Bourdeauducq 2017-07-02 10:24:01 +08:00
parent ea7549cfa4
commit 838127d914
1 changed files with 4 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
artiq/gateware/rtio/dma.py
View File

@ -226,9 +226,9 @@ class TimeOffset(Module, AutoCSR):
# # # # # #
pipe_ce = Signal() self.sync += [
self.sync += \ If(self.source.ack, self.source.stb.eq(0)),
If(pipe_ce, If(~self.source.stb,
self.sink.payload.connect(self.source.payload, self.sink.payload.connect(self.source.payload,
leave_out={"timestamp"}), leave_out={"timestamp"}),
self.source.payload.timestamp.eq(self.sink.payload.timestamp self.source.payload.timestamp.eq(self.sink.payload.timestamp
@ -236,10 +236,8 @@ class TimeOffset(Module, AutoCSR):
self.source.eop.eq(self.sink.eop), self.source.eop.eq(self.sink.eop),
self.source.stb.eq(self.sink.stb) self.source.stb.eq(self.sink.stb)
) )
self.comb += [
pipe_ce.eq(self.source.ack | ~self.source.stb),
self.sink.ack.eq(pipe_ce)
] ]
self.comb += self.sink.ack.eq(~self.source.stb)
class CRIMaster(Module, AutoCSR): class CRIMaster(Module, AutoCSR):