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ad9910: flake8 [nfc] 

Signed-off-by: Robert Jördens <rj@quartiq.de>
This commit is contained in:
Robert Jördens 2018-11-05 19:44:51 +01:00
parent 6d525e2f9a
commit 832690af9a
1 changed files with 26 additions and 21 deletions
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47
artiq/coredevice/ad9910.py
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@ -2,7 +2,7 @@ from numpy import int32, int64
from artiq.language.core import ( from artiq.language.core import (
kernel, delay, portable, delay_mu, now_mu, at_mu) kernel, delay, portable, delay_mu, now_mu, at_mu)
from artiq.language.units import us, ns, ms from artiq.language.units import us, ms
from artiq.coredevice import spi2 as spi from artiq.coredevice import spi2 as spi
from artiq.coredevice import urukul from artiq.coredevice import urukul
@ -72,11 +72,12 @@ class AD9910:
set this to the delay tap number returned. set this to the delay tap number returned.
""" """
kernel_invariants = {"chip_select", "cpld", "core", "bus", kernel_invariants = {"chip_select", "cpld", "core", "bus",
"ftw_per_hz", "pll_n", "io_update_delay", "sysclk_per_mu"} "ftw_per_hz", "pll_n", "io_update_delay",
"sysclk_per_mu"}
def __init__(self, dmgr, chip_select, cpld_device, sw_device=None, def __init__(self, dmgr, chip_select, cpld_device, sw_device=None,
pll_n=40, pll_cp=7, pll_vco=5, sync_delay_seed=-1, pll_n=40, pll_cp=7, pll_vco=5, sync_delay_seed=-1,
io_update_delay=0): io_update_delay=0):
self.cpld = dmgr.get(cpld_device) self.cpld = dmgr.get(cpld_device)
self.core = self.cpld.core self.core = self.cpld.core
self.bus = self.cpld.bus self.bus = self.cpld.bus
@ -95,7 +96,7 @@ class AD9910:
assert self.sysclk_per_mu == sysclk*self.core.ref_period assert self.sysclk_per_mu == sysclk*self.core.ref_period
assert 0 <= pll_vco <= 5 assert 0 <= pll_vco <= 5
vco_min, vco_max = [(370, 510), (420, 590), (500, 700), vco_min, vco_max = [(370, 510), (420, 590), (500, 700),
(600, 880), (700, 950), (820, 1150)][pll_vco] (600, 880), (700, 950), (820, 1150)][pll_vco]
assert vco_min <= sysclk/1e6 <= vco_max assert vco_min <= sysclk/1e6 <= vco_max
self.pll_vco = pll_vco self.pll_vco = pll_vco
assert 0 <= pll_cp <= 7 assert 0 <= pll_cp <= 7
@ -106,7 +107,9 @@ class AD9910:
@kernel @kernel
def set_phase_mode(self, phase_mode): def set_phase_mode(self, phase_mode):
"""Sets the default phase mode for future calls to :meth:`set` and """Set the default phase mode.
for future calls to :meth:`set` and
:meth:`set_mu`. Supported phase modes are: :meth:`set_mu`. Supported phase modes are:
* :const:`PHASE_MODE_CONTINUOUS`: the phase accumulator is unchanged * :const:`PHASE_MODE_CONTINUOUS`: the phase accumulator is unchanged
@ -155,10 +158,10 @@ class AD9910:
:param data: Data to be written :param data: Data to be written
""" """
self.bus.set_config_mu(urukul.SPI_CONFIG, 8, self.bus.set_config_mu(urukul.SPI_CONFIG, 8,
urukul.SPIT_DDS_WR, self.chip_select) urukul.SPIT_DDS_WR, self.chip_select)
self.bus.write(addr << 24) self.bus.write(addr << 24)
self.bus.set_config_mu(urukul.SPI_CONFIG | spi.SPI_END, 32, self.bus.set_config_mu(urukul.SPI_CONFIG | spi.SPI_END, 32,
urukul.SPIT_DDS_WR, self.chip_select) urukul.SPIT_DDS_WR, self.chip_select)
self.bus.write(data) self.bus.write(data)
@kernel @kernel
@ -168,11 +171,11 @@ class AD9910:
:param addr: Register address :param addr: Register address
""" """
self.bus.set_config_mu(urukul.SPI_CONFIG, 8, self.bus.set_config_mu(urukul.SPI_CONFIG, 8,
urukul.SPIT_DDS_WR, self.chip_select) urukul.SPIT_DDS_WR, self.chip_select)
self.bus.write((addr | 0x80) << 24) self.bus.write((addr | 0x80) << 24)
self.bus.set_config_mu(urukul.SPI_CONFIG | spi.SPI_END self.bus.set_config_mu(
| spi.SPI_INPUT, 32, urukul.SPI_CONFIG | spi.SPI_END | spi.SPI_INPUT,
urukul.SPIT_DDS_RD, self.chip_select) 32, urukul.SPIT_DDS_RD, self.chip_select)
self.bus.write(0) self.bus.write(0)
return self.bus.read() return self.bus.read()
@ -185,13 +188,13 @@ class AD9910:
:param data_low: Low (LSB) 32 data bits :param data_low: Low (LSB) 32 data bits
""" """
self.bus.set_config_mu(urukul.SPI_CONFIG, 8, self.bus.set_config_mu(urukul.SPI_CONFIG, 8,
urukul.SPIT_DDS_WR, self.chip_select) urukul.SPIT_DDS_WR, self.chip_select)
self.bus.write(addr << 24) self.bus.write(addr << 24)
self.bus.set_config_mu(urukul.SPI_CONFIG, 32, self.bus.set_config_mu(urukul.SPI_CONFIG, 32,
urukul.SPIT_DDS_WR, self.chip_select) urukul.SPIT_DDS_WR, self.chip_select)
self.bus.write(data_high) self.bus.write(data_high)
self.bus.set_config_mu(urukul.SPI_CONFIG | spi.SPI_END, 32, self.bus.set_config_mu(urukul.SPI_CONFIG | spi.SPI_END, 32,
urukul.SPIT_DDS_WR, self.chip_select) urukul.SPIT_DDS_WR, self.chip_select)
self.bus.write(data_low) self.bus.write(data_low)
@kernel @kernel
@ -305,25 +308,25 @@ class AD9910:
@portable(flags={"fast-math"}) @portable(flags={"fast-math"})
def frequency_to_ftw(self, frequency): def frequency_to_ftw(self, frequency):
"""Returns the frequency tuning word corresponding to the given """Return the frequency tuning word corresponding to the given
frequency. frequency.
""" """
return int32(round(self.ftw_per_hz*frequency)) return int32(round(self.ftw_per_hz*frequency))
@portable(flags={"fast-math"}) @portable(flags={"fast-math"})
def turns_to_pow(self, turns): def turns_to_pow(self, turns):
"""Returns the phase offset word corresponding to the given phase """Return the phase offset word corresponding to the given phase
in turns.""" in turns."""
return int32(round(turns*0x10000)) return int32(round(turns*0x10000))
@portable(flags={"fast-math"}) @portable(flags={"fast-math"})
def amplitude_to_asf(self, amplitude): def amplitude_to_asf(self, amplitude):
"""Returns amplitude scale factor corresponding to given amplitude.""" """Return amplitude scale factor corresponding to given amplitude."""
return int32(round(amplitude*0x3ffe)) return int32(round(amplitude*0x3ffe))
@portable(flags={"fast-math"}) @portable(flags={"fast-math"})
def pow_to_turns(self, pow): def pow_to_turns(self, pow):
"""Returns the phase in turns corresponding to a given phase offset """Return the phase in turns corresponding to a given phase offset
word.""" word."""
return pow/0x10000 return pow/0x10000
@ -397,7 +400,8 @@ class AD9910:
@kernel @kernel
def clear_smp_err(self): def clear_smp_err(self):
"""Clears the SMP_ERR flag and enables SMP_ERR validity monitoring. """Clear the SMP_ERR flag and enables SMP_ERR validity monitoring.
Violations of the SYNC_IN sample and hold margins will result in Violations of the SYNC_IN sample and hold margins will result in
SMP_ERR being asserted. This then also activates the red LED on SMP_ERR being asserted. This then also activates the red LED on
the respective Urukul channel. the respective Urukul channel.
@ -513,7 +517,8 @@ class AD9910:
d0 = self.io_update_delay d0 = self.io_update_delay
t0 = int32(self.measure_io_update_alignment(d0)) t0 = int32(self.measure_io_update_alignment(d0))
for i in range(max_delay - 1): for i in range(max_delay - 1):
t = self.measure_io_update_alignment((d0 + i + 1) & (max_delay - 1)) t = self.measure_io_update_alignment(
(d0 + i + 1) & (max_delay - 1))
if t != t0: if t != t0:
return (d0 + i + period//2) & (period - 1) return (d0 + i + period//2) & (period - 1)
raise ValueError("no IO_UPDATE-SYNC_CLK alignment edge found") raise ValueError("no IO_UPDATE-SYNC_CLK alignment edge found")