diff --git a/artiq/build_soc.py b/artiq/build_soc.py index bdf652948..f51c8885a 100644 --- a/artiq/build_soc.py +++ b/artiq/build_soc.py @@ -59,16 +59,16 @@ def build_artiq_soc(soc, argdict): builder.software_packages = [] builder.add_software_package("bootloader", os.path.join(firmware_dir, "bootloader")) is_kasli_v1 = isinstance(soc.platform, kasli.Platform) and soc.platform.hw_rev in ("v1.0", "v1.1") - if isinstance(soc, AMPSoC): - kernel_cpu_type = "vexriscv" if is_kasli_v1 else "vexriscv-g" - builder.add_software_package("libm", cpu_type=kernel_cpu_type) - builder.add_software_package("libprintf", cpu_type=kernel_cpu_type) - builder.add_software_package("libunwind", cpu_type=kernel_cpu_type) - builder.add_software_package("ksupport", os.path.join(firmware_dir, "ksupport"), cpu_type=kernel_cpu_type) - # Generate unwinder for soft float target (ARTIQ runtime) - # If the kernel lacks FPU, then the runtime unwinder is already generated - if not is_kasli_v1: - builder.add_software_package("libunwind") + kernel_cpu_type = "vexriscv" if is_kasli_v1 else "vexriscv-g" + builder.add_software_package("libm", cpu_type=kernel_cpu_type) + builder.add_software_package("libprintf", cpu_type=kernel_cpu_type) + builder.add_software_package("libunwind", cpu_type=kernel_cpu_type) + builder.add_software_package("ksupport", os.path.join(firmware_dir, "ksupport"), cpu_type=kernel_cpu_type) + # Generate unwinder for soft float target (ARTIQ runtime) + # If the kernel lacks FPU, then the runtime unwinder is already generated + if not is_kasli_v1: + builder.add_software_package("libunwind") + if not soc.config["DRTIO_ROLE"] == "satellite": builder.add_software_package("runtime", os.path.join(firmware_dir, "runtime")) else: # Assume DRTIO satellite. diff --git a/artiq/gateware/amp/soc.py b/artiq/gateware/amp/soc.py index 91b75ca3a..baba52151 100644 --- a/artiq/gateware/amp/soc.py +++ b/artiq/gateware/amp/soc.py @@ -36,6 +36,7 @@ class AMPSoC: csrs = getattr(self, name).get_csrs() csr_bus = wishbone.Interface(data_width=32, adr_width=32-log2_int(self.csr_separation)) bank = wishbone.CSRBank(csrs, bus=csr_bus) + self.config["kernel_has_"+name] = None self.submodules += bank self.kernel_cpu.add_wb_slave(self.mem_map[name], self.csr_separation*2**bank.decode_bits, bank.bus) self.add_csr_region(name, diff --git a/artiq/gateware/targets/kasli.py b/artiq/gateware/targets/kasli.py index d292d37d9..55baa6a03 100755 --- a/artiq/gateware/targets/kasli.py +++ b/artiq/gateware/targets/kasli.py @@ -406,9 +406,11 @@ class MasterBase(MiniSoC, AMPSoC): self.drtio_qpll_channel, self.ethphy_qpll_channel = qpll.channels -class SatelliteBase(BaseSoC): +class SatelliteBase(BaseSoC, AMPSoC): mem_map = { - "drtioaux": 0x50000000, + "rtio": 0x20000000, + "drtioaux": 0x50000000, + "mailbox": 0x70000000 } mem_map.update(BaseSoC.mem_map) @@ -417,6 +419,7 @@ class SatelliteBase(BaseSoC): cpu_bus_width = 32 else: cpu_bus_width = 64 + BaseSoC.__init__(self, cpu_type="vexriscv", hw_rev=hw_rev, @@ -426,6 +429,7 @@ class SatelliteBase(BaseSoC): clk_freq=rtio_clk_freq, rtio_sys_merge=True, **kwargs) + AMPSoC.__init__(self) add_identifier(self, gateware_identifier_str=gateware_identifier_str) platform = self.platform @@ -439,7 +443,7 @@ class SatelliteBase(BaseSoC): cdr_clk_out = self.platform.request("cdr_clk_clean") else: cdr_clk_out = self.platform.request("si5324_clkout") - + cdr_clk = Signal() self.platform.add_period_constraint(cdr_clk_out, 8.) @@ -574,12 +578,18 @@ class SatelliteBase(BaseSoC): self.submodules.rtio_moninj = rtio.MonInj(rtio_channels) self.csr_devices.append("rtio_moninj") + # satellite (master-controlled) RTIO self.submodules.local_io = SyncRTIO(self.rtio_tsc, rtio_channels, lane_count=sed_lanes) self.comb += self.drtiosat.async_errors.eq(self.local_io.async_errors) + + # subkernel RTIO + self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc) + self.register_kernel_cpu_csrdevice("rtio") + self.submodules.rtio_dma = rtio.DMA(self.get_native_sdram_if(), self.cpu_dw) self.csr_devices.append("rtio_dma") self.submodules.cri_con = rtio.CRIInterconnectShared( - [self.drtiosat.cri, self.rtio_dma.cri], + [self.drtiosat.cri, self.rtio_dma.cri, self.rtio.cri], [self.local_io.cri] + self.drtio_cri, enable_routing=True) self.csr_devices.append("cri_con") diff --git a/artiq/gateware/targets/kasli_generic.py b/artiq/gateware/targets/kasli_generic.py index 3fc50b661..ad07a9e7a 100755 --- a/artiq/gateware/targets/kasli_generic.py +++ b/artiq/gateware/targets/kasli_generic.py @@ -22,7 +22,7 @@ class GenericStandalone(StandaloneBase): hw_rev = description["hw_rev"] self.class_name_override = description["variant"] StandaloneBase.__init__(self, hw_rev=hw_rev, **kwargs) - + self.config["DRTIO_ROLE"] = description["base"] self.config["RTIO_FREQUENCY"] = "{:.1f}".format(description["rtio_frequency"]/1e6) if "ext_ref_frequency" in description: self.config["SI5324_EXT_REF"] = None @@ -76,6 +76,7 @@ class GenericMaster(MasterBase): rtio_clk_freq=description["rtio_frequency"], enable_sata=description["enable_sata_drtio"], **kwargs) + self.config["DRTIO_ROLE"] = description["base"] if "ext_ref_frequency" in description: self.config["SI5324_EXT_REF"] = None self.config["EXT_REF_FREQUENCY"] = "{:.1f}".format( @@ -113,6 +114,7 @@ class GenericSatellite(SatelliteBase): rtio_clk_freq=description["rtio_frequency"], enable_sata=description["enable_sata_drtio"], **kwargs) + self.config["DRTIO_ROLE"] = description["base"] if hw_rev == "v1.0": # EEM clock fan-out from Si5324, not MMCX self.comb += self.platform.request("clk_sel").eq(1) diff --git a/artiq/gateware/targets/kc705.py b/artiq/gateware/targets/kc705.py index 251b56661..884586f07 100755 --- a/artiq/gateware/targets/kc705.py +++ b/artiq/gateware/targets/kc705.py @@ -98,6 +98,8 @@ class _StandaloneBase(MiniSoC, AMPSoC): AMPSoC.__init__(self) add_identifier(self, gateware_identifier_str=gateware_identifier_str) + self.config["DRTIO_ROLE"] = "standalone" + if isinstance(self.platform.toolchain, XilinxVivadoToolchain): self.platform.toolchain.bitstream_commands.extend([ "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]", @@ -194,6 +196,8 @@ class _MasterBase(MiniSoC, AMPSoC): AMPSoC.__init__(self) add_identifier(self, gateware_identifier_str=gateware_identifier_str) + self.config["DRTIO_ROLE"] = "master" + if isinstance(self.platform.toolchain, XilinxVivadoToolchain): self.platform.toolchain.bitstream_commands.extend([ "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]", @@ -314,9 +318,11 @@ class _MasterBase(MiniSoC, AMPSoC): -class _SatelliteBase(BaseSoC): +class _SatelliteBase(BaseSoC, AMPSoC): mem_map = { + "rtio": 0x20000000, "drtioaux": 0x50000000, + "mailbox": 0x70000000 } mem_map.update(BaseSoC.mem_map) @@ -331,8 +337,11 @@ class _SatelliteBase(BaseSoC): clk_freq=clk_freq, rtio_sys_merge=True, **kwargs) + AMPSoC.__init__(self) add_identifier(self, gateware_identifier_str=gateware_identifier_str) + self.config["DRTIO_ROLE"] = "satellite" + if isinstance(self.platform.toolchain, XilinxVivadoToolchain): self.platform.toolchain.bitstream_commands.extend([ "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]", @@ -453,12 +462,18 @@ class _SatelliteBase(BaseSoC): self.submodules.rtio_moninj = rtio.MonInj(rtio_channels) self.csr_devices.append("rtio_moninj") + # DRTIO self.submodules.local_io = SyncRTIO(self.rtio_tsc, rtio_channels) self.comb += self.drtiosat.async_errors.eq(self.local_io.async_errors) + + # subkernel RTIO + self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc) + self.register_kernel_cpu_csrdevice("rtio") + self.submodules.rtio_dma = rtio.DMA(self.get_native_sdram_if(), self.cpu_dw) self.csr_devices.append("rtio_dma") self.submodules.cri_con = rtio.CRIInterconnectShared( - [self.drtiosat.cri, self.rtio_dma.cri], + [self.drtiosat.cri, self.rtio_dma.cri, self.rtio.cri], [self.local_io.cri] + self.drtio_cri, enable_routing=True) self.csr_devices.append("cri_con")