From 8280e72e90522f77d6d4f4671d829f9089071f85 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sat, 24 Sep 2016 20:48:37 +0800 Subject: [PATCH] gateware: use new misoc CSR mapping API --- artiq/gateware/soc.py | 4 +--- artiq/gateware/targets/kc705.py | 16 ++++------------ artiq/gateware/targets/pipistrello.py | 12 +++--------- 3 files changed, 8 insertions(+), 24 deletions(-) diff --git a/artiq/gateware/soc.py b/artiq/gateware/soc.py index b1b84f25e..cd567b305 100644 --- a/artiq/gateware/soc.py +++ b/artiq/gateware/soc.py @@ -26,6 +26,7 @@ class AMPSoC: self.submodules.kernel_cpu = amp.KernelCPU(self.platform) self.add_cpulevel_sdram_if(self.kernel_cpu.wb_sdram) + self.csr_devices.append("kernel_cpu") self.submodules.mailbox = amp.Mailbox() self.add_wb_slave(mem_decoder(self.mem_map["mailbox"]), @@ -39,9 +40,6 @@ class AMPSoC: self.register_kernel_cpu_csrdevice("timer_kernel") def register_kernel_cpu_csrdevice(self, name): - # make sure the device is not getting connected to the comms-CPU already - assert self.csr_map[name] is None - csrs = getattr(self, name).get_csrs() bank = wishbone.CSRBank(csrs) self.submodules += bank diff --git a/artiq/gateware/targets/kc705.py b/artiq/gateware/targets/kc705.py index 1403ec14b..7209a2b3b 100755 --- a/artiq/gateware/targets/kc705.py +++ b/artiq/gateware/targets/kc705.py @@ -101,18 +101,6 @@ _ams101_dac = [ class _NIST_Ions(MiniSoC, AMPSoC): - csr_map = { - # mapped on Wishbone instead - "timer_kernel": None, - "rtio": None, - "i2c": None, - - "rtio_crg": 13, - "kernel_cpu": 14, - "rtio_moninj": 15, - "rtio_analyzer": 16 - } - csr_map.update(MiniSoC.csr_map) mem_map = { "timer_kernel": 0x10000000, # (shadow @0x90000000) "rtio": 0x20000000, # (shadow @0xa0000000) @@ -140,6 +128,7 @@ class _NIST_Ions(MiniSoC, AMPSoC): self.submodules.leds = gpio.GPIOOut(Cat( self.platform.request("user_led", 0), self.platform.request("user_led", 1))) + self.csr_devices.append("leds") self.platform.add_extension(_sma33_io) self.platform.add_extension(_ams101_dac) @@ -151,10 +140,12 @@ class _NIST_Ions(MiniSoC, AMPSoC): def add_rtio(self, rtio_channels): self.submodules.rtio_crg = _RTIOCRG(self.platform, self.crg.cd_sys.clk) + self.csr_devices.append("rtio_crg") self.submodules.rtio = rtio.RTIO(rtio_channels) self.register_kernel_cpu_csrdevice("rtio") self.config["RTIO_FINE_TS_WIDTH"] = self.rtio.fine_ts_width self.submodules.rtio_moninj = rtio.MonInj(rtio_channels) + self.csr_devices.append("rtio_moninj") self.specials += [ Keep(self.rtio.cd_rsys.clk), @@ -175,6 +166,7 @@ class _NIST_Ions(MiniSoC, AMPSoC): self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio, self.get_native_sdram_if()) + self.csr_devices.append("rtio_analyzer") class NIST_QC1(_NIST_Ions): diff --git a/artiq/gateware/targets/pipistrello.py b/artiq/gateware/targets/pipistrello.py index 98e6555bb..f9afa683b 100755 --- a/artiq/gateware/targets/pipistrello.py +++ b/artiq/gateware/targets/pipistrello.py @@ -125,15 +125,6 @@ TIMESPEC "TSfix_ise4" = FROM "GRPsys_clk" TO "GRPrtio_clk" TIG; class NIST_QC1(BaseSoC, AMPSoC): - csr_map = { - "timer_kernel": None, # mapped on Wishbone instead - "rtio": None, # mapped on Wishbone instead - "rtio_crg": 10, - "kernel_cpu": 11, - "rtio_moninj": 12, - "rtio_analyzer": 13 - } - csr_map.update(BaseSoC.csr_map) mem_map = { "timer_kernel": 0x10000000, # (shadow @0x90000000) "rtio": 0x20000000, # (shadow @0xa0000000) @@ -168,6 +159,7 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd ] self.submodules.rtio_crg = _RTIOCRG(platform, self.clk_freq) + self.csr_devices.append("rtio_crg") # RTIO channels rtio_channels = [] @@ -235,8 +227,10 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd self.config["RTIO_FINE_TS_WIDTH"] = self.rtio.fine_ts_width self.config["DDS_RTIO_CLK_RATIO"] = 8 >> self.rtio.fine_ts_width self.submodules.rtio_moninj = rtio.MonInj(rtio_channels) + self.csr_devices.append("rtio_moninj") self.submodules.rtio_analyzer = rtio.Analyzer( self.rtio, self.get_native_sdram_if()) + self.csr_devices.append("rtio_analyzer") def main():