From 825c49a9110bf2f7828339518f02631673d8fe8d Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Sun, 30 Apr 2023 16:43:52 +0800
Subject: [PATCH] artiq_ddb_template: fix pll_en typing

---
 artiq/coredevice/coredevice_generic.schema.json | 12 ++++--------
 artiq/frontend/artiq_ddb_template.py            |  6 +++---
 2 files changed, 7 insertions(+), 11 deletions(-)

diff --git a/artiq/coredevice/coredevice_generic.schema.json b/artiq/coredevice/coredevice_generic.schema.json
index e11ba4976..c7e74c68e 100644
--- a/artiq/coredevice/coredevice_generic.schema.json
+++ b/artiq/coredevice/coredevice_generic.schema.json
@@ -303,10 +303,8 @@
                             "type": "integer"
                         },
                         "pll_en": {
-                            "type": "integer",
-                            "minimum": 0,
-                            "maximum": 1,
-                            "default": 1
+                            "type": "boolean",
+                            "default": true
                         },
                         "pll_vco": {
                             "type": "integer"
@@ -372,10 +370,8 @@
                             "default": 32
                         },
                         "pll_en": {
-                            "type": "integer",
-                            "minimum": 0,
-                            "maximum": 1,
-                            "default": 1
+                            "type": "boolean",
+                            "default": true
                         },
                         "pll_vco": {
                             "type": "integer"
diff --git a/artiq/frontend/artiq_ddb_template.py b/artiq/frontend/artiq_ddb_template.py
index ab9762814..9322e7f50 100755
--- a/artiq/frontend/artiq_ddb_template.py
+++ b/artiq/frontend/artiq_ddb_template.py
@@ -260,7 +260,7 @@ class PeripheralManager:
                     uchn=i,
                     sw=",\n        \"sw_device\": \"ttl_{name}_sw{uchn}\"".format(name=urukul_name, uchn=i) if len(peripheral["ports"]) > 1 else "",
                     pll_vco=",\n        \"pll_vco\": {}".format(pll_vco) if pll_vco is not None else "",
-                    pll_n=peripheral.get("pll_n", 32), pll_en=peripheral.get("pll_en", 1),
+                    pll_n=peripheral.get("pll_n", 32), pll_en=peripheral.get("pll_en", True),
                     sync_delay_seed=",\n        \"sync_delay_seed\": \"eeprom_{}:{}\"".format(urukul_name, 64 + 4*i) if synchronization else "",
                     io_update_delay=",\n        \"io_update_delay\": \"eeprom_{}:{}\"".format(urukul_name, 64 + 4*i) if synchronization else "")
             elif dds == "ad9912":
@@ -281,7 +281,7 @@ class PeripheralManager:
                     uchn=i,
                     sw=",\n        \"sw_device\": \"ttl_{name}_sw{uchn}\"".format(name=urukul_name, uchn=i) if len(peripheral["ports"]) > 1 else "",
                     pll_vco=",\n        \"pll_vco\": {}".format(pll_vco) if pll_vco is not None else "",
-                    pll_n=peripheral.get("pll_n", 8), pll_en=peripheral.get("pll_en", 1))
+                    pll_n=peripheral.get("pll_n", 8), pll_en=peripheral.get("pll_en", True))
             else:
                 raise ValueError
         return next(channel)
@@ -475,7 +475,7 @@ class PeripheralManager:
                 refclk=peripheral.get("refclk", self.master_description["rtio_frequency"]),
                 clk_sel=peripheral["clk_sel"],
                 pll_vco=",\n        \"pll_vco\": {}".format(pll_vco) if pll_vco is not None else "",
-                pll_n=peripheral["pll_n"],  pll_en=peripheral.get("pll_en", 1))
+                pll_n=peripheral["pll_n"],  pll_en=peripheral.get("pll_en", True))
         return next(channel)
 
     def process_zotino(self, rtio_offset, peripheral):