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hmc7043: improve smoothness of sysref phase control

This commit is contained in:
Sebastien Bourdeauducq 2018-06-20 17:40:48 +08:00
parent 9142a5ab8a
commit 814d0583db
2 changed files with 7 additions and 5 deletions
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2
artiq/firmware/libboard_artiq/ad9154.rs
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@ -757,7 +757,7 @@ fn init_dac(dacno: u8) -> Result<(), &'static str> {
// Run the PRBS, STPL and SYSREF scan tests // Run the PRBS, STPL and SYSREF scan tests
dac_prbs(dacno)?; dac_prbs(dacno)?;
dac_stpl(dacno, 4, 2)?; dac_stpl(dacno, 4, 2)?;
let sysref_phase = 58; let sysref_phase = 61;
dac_sysref_scan(dacno, sysref_phase); dac_sysref_scan(dacno, sysref_phase);
// Set SYSREF phase and reconfigure the DAC // Set SYSREF phase and reconfigure the DAC
dac_sysref_cfg(dacno, sysref_phase); dac_sysref_cfg(dacno, sysref_phase);

10
artiq/firmware/libboard_artiq/hmc830_7043.rs
View File

@ -318,12 +318,14 @@ pub mod hmc7043 {
* Digital delay resolution: 1/2 input clock cycle = 416ps for 1.2GHz * Digital delay resolution: 1/2 input clock cycle = 416ps for 1.2GHz
* 16*25ps = 400ps: limit analog delay to 16 steps instead of 32. * 16*25ps = 400ps: limit analog delay to 16 steps instead of 32.
*/ */
let analog_delay = (phase % 17) as u8;
let digital_delay = (phase / 17) as u8;
if dacno == 0 { if dacno == 0 {
write(0x00d5, (phase & 0xf) as u8); write(0x00d5, analog_delay);
write(0x00d6, ((phase >> 4) & 0x1f) as u8); write(0x00d6, digital_delay);
} else if dacno == 1 { } else if dacno == 1 {
write(0x00e9, (phase & 0xf) as u8); write(0x00e9, analog_delay);
write(0x00ea, ((phase >> 4) & 0x1f) as u8); write(0x00ea, digital_delay);
} else { } else {
unimplemented!(); unimplemented!();
} }