mirror of https://github.com/m-labs/artiq.git
coredevice: set default pow for ad9912 set_mu()
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@ -156,7 +156,7 @@ class AD9912:
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return self.cpld.get_channel_att(self.chip_select - 4)
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return self.cpld.get_channel_att(self.chip_select - 4)
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@kernel
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@kernel
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def set_mu(self, ftw: TInt64, pow_: TInt32):
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def set_mu(self, ftw: TInt64, pow_: TInt32 = 0):
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"""Set profile 0 data in machine units.
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"""Set profile 0 data in machine units.
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After the SPI transfer, the shared IO update pin is pulsed to
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After the SPI transfer, the shared IO update pin is pulsed to
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