kc705.clock: add all spi buses

2016-03-04 00:03:48 +01:00 · 2016-03-04 00:03:48 +01:00 · 7ff0c89d51
parent 669fbaa4f1
commit 7ff0c89d51
1 changed files with 1 additions and 1 deletions
--- a/artiq/gateware/targets/kc705.py
+++ b/artiq/gateware/targets/kc705.py
@ -264,7 +264,7 @@ class NIST_CLOCK(_NIST_Ions):
        rtio_channels.append(rtio.Channel.from_phy(
            phy, ofifo_depth=4, ififo_depth=4))

-        for i in range(1):  # spi1 and spi2 collide in pinout with ttl
+        for i in range(3):
            phy = spi.SPIMaster(self.platform.request("spi", i))
            self.submodules += phy
            rtio_channels.append(rtio.Channel.from_phy(