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kc705.clock: add all spi buses
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@ -264,7 +264,7 @@ class NIST_CLOCK(_NIST_Ions):
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rtio_channels.append(rtio.Channel.from_phy(
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phy, ofifo_depth=4, ififo_depth=4))
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for i in range(1): # spi1 and spi2 collide in pinout with ttl
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for i in range(3):
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phy = spi.SPIMaster(self.platform.request("spi", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(
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