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disable DRTIO-over-EEM OSERDES until clock is stable 

This asserts OOB reset on EFC.
pull/2191/head
occheung 2023-09-05 16:58:28 +08:00 committed by Sebastien Bourdeauducq
parent 5e5d671f4c
commit 7f63bb322d
3 changed files with 14 additions and 1 deletions
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3
artiq/firmware/runtime/rtio_clocking.rs
View File

@ -267,6 +267,9 @@ pub fn init() {
// enable TX after the reboot, with stable clock
unsafe {
csr::gt_drtio::txenable_write(0xffffffffu32 as _);
#[cfg(has_drtio_eem)]
csr::eem_transceiver::txenable_write(0xffffffffu32 as _);
}
}
}

5
artiq/firmware/satman/main.rs
View File

@ -556,6 +556,11 @@ pub extern fn main() -> i32 {
csr::gt_drtio::txenable_write(0xffffffffu32 as _);
}
#[cfg(has_drtio_eem)]
unsafe {
csr::eem_transceiver::txenable_write(0xffffffffu32 as _);
}
init_rtio_crg();
#[cfg(has_drtio_eem)]

7
artiq/gateware/drtio/transceiver/eem_serdes.py
View File

@ -109,6 +109,8 @@ class TXSerdes(Module):
ser_out = [ Signal() for _ in range(4) ]
t_out = [ Signal() for _ in range(4) ]
self.ext_rst = Signal()
for i in range(4):
self.specials += [
# Serializer
@ -118,7 +120,7 @@ class TXSerdes(Module):
p_INIT_OQ=0b00000,
o_OQ=ser_out[i],
o_TQ=t_out[i],
i_RST=ResetSignal(),
i_RST=ResetSignal() | self.ext_rst,
i_CLK=ClockSignal("sys5x"),
i_CLKDIV=ClockSignal(),
i_D1=self.txdata[i][0],
@ -529,3 +531,6 @@ class EEMSerdes(Module, TransceiverInterface, AutoCSR):
self.rst.attr.add("no_retiming")
TransceiverInterface.__init__(self, channel_interfaces, async_rx=False)
for tx_en, serdes in zip(self.txenable.storage, serdes_list):
self.comb += serdes.tx_serdes.ext_rst.eq(~tx_en)