From 7ef21f03b98e5af196f080a19456500a75fc9aeb Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Mon, 29 Feb 2016 22:19:39 +0100 Subject: [PATCH] nist_clock: add SPIMasters to spi buses --- artiq/gateware/targets/kc705.py | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/artiq/gateware/targets/kc705.py b/artiq/gateware/targets/kc705.py index 39a8ae3b2..5213adaae 100755 --- a/artiq/gateware/targets/kc705.py +++ b/artiq/gateware/targets/kc705.py @@ -250,18 +250,24 @@ class NIST_CLOCK(_NIST_Ions): self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) - spi_pins = self.platform.request("ams101_dac", 0) - phy = ttl_simple.Output(spi_pins.ldac) + ams101_dac = self.platform.request("ams101_dac", 0) + phy = ttl_simple.Output(ams101_dac.ldac) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) self.config["RTIO_REGULAR_TTL_COUNT"] = len(rtio_channels) - phy = spi.SPIMaster(spi_pins) + phy = spi.SPIMaster(ams101_dac) self.submodules += phy self.config["RTIO_FIRST_SPI_CHANNEL"] = len(rtio_channels) rtio_channels.append(rtio.Channel.from_phy( phy, ofifo_depth=4, ififo_depth=4)) + for i in range(3): + phy = spi.SPIMaster(self.platform.request("spi", i)) + self.submodules += phy + rtio_channels.append(rtio.Channel.from_phy( + phy, ofifo_depth=128, ififo_depth=128)) + phy = ttl_simple.ClockGen(platform.request("la32_p")) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy))