From 7e5c062c2c61edddef9601b6dfe4bc85007a265b Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sun, 27 Jan 2019 11:49:34 +0800 Subject: [PATCH] firmware: bypass channel divider for HMC7043 DCLK --- artiq/firmware/libboard_artiq/hmc830_7043.rs | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/artiq/firmware/libboard_artiq/hmc830_7043.rs b/artiq/firmware/libboard_artiq/hmc830_7043.rs index 56435807d..c425d71d5 100644 --- a/artiq/firmware/libboard_artiq/hmc830_7043.rs +++ b/artiq/firmware/libboard_artiq/hmc830_7043.rs @@ -159,8 +159,9 @@ pub mod hmc7043 { use board_misoc::{csr, clock}; // Warning: dividers are not synchronized with HMC830 clock input! - // Set DAC_CLK_DIV to 1 for deterministic phase. - pub const DAC_CLK_DIV: u16 = 1; // 2400MHz + // Set DAC_CLK_DIV to 1 or 0 for deterministic phase. + // (0 bypasses the divider and reduces noise) + pub const DAC_CLK_DIV: u16 = 0; // 2400MHz pub const FPGA_CLK_DIV: u16 = 16; // 150MHz pub const SYSREF_DIV: u16 = 256; // 9.375MHz const HMC_SYSREF_DIV: u16 = SYSREF_DIV*8; // 1.171875MHz (must be <= 4MHz)