From 57ce78c54db4ecc817c3e814dcbfcb5112599cf1 Mon Sep 17 00:00:00 2001
From: Robert Jordens <jordens@gmail.com>
Date: Mon, 18 Jan 2016 19:17:44 -0700
Subject: [PATCH] pipistrello: add rtio.Analyzer()

---
 artiq/gateware/targets/pipistrello.py | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/artiq/gateware/targets/pipistrello.py b/artiq/gateware/targets/pipistrello.py
index 450d6fa5d..c6290d2ac 100755
--- a/artiq/gateware/targets/pipistrello.py
+++ b/artiq/gateware/targets/pipistrello.py
@@ -106,7 +106,8 @@ class NIST_QC1(BaseSoC, AMPSoC):
         "rtio": None,  # mapped on Wishbone instead
         "rtio_crg": 10,
         "kernel_cpu": 11,
-        "rtio_moninj": 12
+        "rtio_moninj": 12,
+        "rtio_analyzer": 13
     }
     csr_map.update(BaseSoC.csr_map)
     mem_map = {
@@ -208,6 +209,9 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
         self.add_csr_region("rtio", self.mem_map["rtio"] | 0x80000000, 32,
                             rtio_csrs)
 
+        self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio,
+            self.get_native_sdram_if())
+
 
 def main():
     parser = argparse.ArgumentParser(